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TMC2302AH5C

Description
Image Manipulation Sequencer
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size192KB,36 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric Compare View All

TMC2302AH5C Overview

Image Manipulation Sequencer

TMC2302AH5C Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codePGA
package instructionPGA, PGA120,13X13
Contacts120
Reach Compliance Codeunknow
ECCN code3A991.A.2
boundary scanNO
maximum clock frequency30.3 MHz
External data bus width16
JESD-30 codeS-PPGA-P120
JESD-609 codee0
length34.544 mm
low power modeNO
Number of terminals120
Maximum operating temperature70 °C
Minimum operating temperature
Output data bus width12
Package body materialPLASTIC/EPOXY
encapsulated codePGA
Encapsulate equivalent codePGA120,13X13
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height5.461 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperatureNOT SPECIFIED
width34.544 mm
uPs/uCs/peripheral integrated circuit typeDSP PERIPHERAL, ADDRESS SEQUENCER
Base Number Matches1
www.fairchildsemi.com
TMC2302A
Image Manipulation Sequencer
40 MHz
Features
• Asynchronous loading of control parameters
• Rapid (25ns per pixel) rotation, warping, panning, and
scaling of images
• Three-dimensional image addressing capability
• General third-order polynomial transformations in two
dimensions on-chip
• Three-dimensional transformation of up to order 1.5 also
supported
• Flexible, user-configurable pixel datapath timing structure
• Static convolutional filtering of up to 16 x 16 Pixel (one-
pass), 256 x 256 pixel (two-pass) or 256 x 256 x 256 pixel
(three-pass) windows
• User-selectable source image subpixel resolution of
2
-8
to 2
-16
• Pin-compatible upgrade to TMC2302
• 24-bit (optional 36-bit) positioning precision within the
source image space, 48-bit internal precision
• Low power CMOS process
• Available in a 120-pin Plastic Pin Grid Array and 120-lead
Metric Quad Flat Pack
Applications
High-performance video special-effects generators
Guidance systems
Image recognition
Robotics
High-precision image registration
Preliminary Information
Description
The TMC2302A, a pin-compatible replacement for the
TMC2302, is a high-speed self-sequencing address genera-
tor which supports image manipulations such as rotation,
rescaling, warping, filtering, and resampling. It remaps the
pixel locations of a target (display) space back into those of a
source image space. The degree and type of image manipula-
tion is determined by the remapping selected.
To remap from the target to the source space, this integrated
circuit computes a series of polynomials of the target space
coordinates, based on user-assigned coefficients. Two
TMC2302A chips can generate third-order warps of a two-
dimensional image, whereas three can second-order warp a
three-dimensional image.
Simplified Block Diagram
OES
IDAT
15-0
ASYNCHRONOUS
HOST INTERFACE
IADR
6-0
ICS
IWR
WALK
COUNTER
SYNC
NOOP
SYNCHRONOUS
HOST INTERFACE
INIT
CONTROL
PARAMETER
REGISTERS
SOURCE
ADDRESS
GENERATOR
SADR
23-0
SVAL
OEK
KADR
7-0
ACC
TWR
OET
CONTROL
TARGET
ADDRESS
GENERATOR
TADR
11-0
TVAL
END
SYNC FLAGS
DONE
65-2302-01
SOURCE MEMORY
INTERFACE
CONVOLUTIONAL
CONTROL
TARGET
MEMORY
INTERFACE
CLK
Rev. 0.9.2

TMC2302AH5C Related Products

TMC2302AH5C TMC2302A TMC2302AH5C1 TMC2302AKEC TMC2302AKEC1
Description Image Manipulation Sequencer Image Manipulation Sequencer Image Manipulation Sequencer Image Manipulation Sequencer Image Manipulation Sequencer
Is it Rohs certified? incompatible - incompatible incompatible incompatible
Parts packaging code PGA - PGA QFP QFP
package instruction PGA, PGA120,13X13 - PGA, PGA120,13X13 QFP, QFP120,1.2SQ,32 QFP, QFP120,1.2SQ,32
Contacts 120 - 120 120 120
Reach Compliance Code unknow - unknow unknow unknow
ECCN code 3A991.A.2 - 3A991.A.2 3A991.A.2 3A991.A.2
boundary scan NO - NO NO NO
maximum clock frequency 30.3 MHz - 40 MHz 30.3 MHz 40 MHz
External data bus width 16 - 16 16 16
JESD-30 code S-PPGA-P120 - S-PPGA-P120 S-PQFP-G120 S-PQFP-G120
JESD-609 code e0 - e0 e0 e0
length 34.544 mm - 34.544 mm 28 mm 28 mm
low power mode NO - NO NO NO
Number of terminals 120 - 120 120 120
Maximum operating temperature 70 °C - 70 °C 70 °C 70 °C
Output data bus width 12 - 12 12 12
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code PGA - PGA QFP QFP
Encapsulate equivalent code PGA120,13X13 - PGA120,13X13 QFP120,1.2SQ,32 QFP120,1.2SQ,32
Package shape SQUARE - SQUARE SQUARE SQUARE
Package form GRID ARRAY - GRID ARRAY FLATPACK FLATPACK
Peak Reflow Temperature (Celsius) NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
power supply 5 V - 5 V 5 V 5 V
Certification status Not Qualified - Not Qualified Not Qualified Not Qualified
Maximum seat height 5.461 mm - 5.461 mm 3.92 mm 3.92 mm
Maximum supply voltage 5.25 V - 5.25 V 5.25 V 5.25 V
Minimum supply voltage 4.75 V - 4.75 V 4.75 V 4.75 V
Nominal supply voltage 5 V - 5 V 5 V 5 V
surface mount NO - NO YES YES
technology CMOS - CMOS CMOS CMOS
Temperature level COMMERCIAL - COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form PIN/PEG - PIN/PEG GULL WING GULL WING
Terminal pitch 2.54 mm - 2.54 mm 0.8 mm 0.8 mm
Terminal location PERPENDICULAR - PERPENDICULAR QUAD QUAD
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 34.544 mm - 34.544 mm 28 mm 28 mm
uPs/uCs/peripheral integrated circuit type DSP PERIPHERAL, ADDRESS SEQUENCER - DSP PERIPHERAL, ADDRESS SEQUENCER DSP PERIPHERAL, ADDRESS SEQUENCER DSP PERIPHERAL, ADDRESS SEQUENCER
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