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P1020RDB-PD

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development boards & kits - other processors p1020rdb-PD
CategoryDevelopment board/suite/development tools   
File Size493KB,16 Pages
ManufacturerFREESCALE (NXP)
Environmental Compliance  
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development boards & kits - other processors p1020rdb-PD

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ManufactureFreescale Semiconduc
Product CategoryDevelopment Boards & Kits - Other Processors
Freescale Semiconductor
Product Brief
Document Number: P1020PB
Rev. 0, 11/2008
This document contains
preview information on a new
product that may be in a design
phase or under development.
Freescale reserves the right to
change or discontinue this
product without notice.
QorIQ™ P1020
Integrated Processor
Product Brief
This document provides an overview of features and
functionality of the QorIQ™ P1020 integrated processor.
The P1020 combines dual Power Architecture™ e500v2
processor cores with system logic required for
networking, wireless infrastructure, and
telecommunications applications.
The P1020 offers an excellent combination of protocol
and interface support including dual high-performance
CPU cores, an L2 cache, a DDR2/DDR3 memory
controller, three enhanced three-speed Ethernet
controllers with support for SGMII and for
IEEE Std 1588™ precision time protocol for network
synchronization over Ethernet, a TDM interface, two
USB 2.0 interface, an independent SD/MMC card
controller (eSDHC), integrated system performance
monitor, and two PCI Express controllers.
Contents
1
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Dual-Core Device Application . . . . . . . . . . . . . . . . . 2
1.2 High-Performance Communication System . . . . . . 4
1.3 RAID Controller Application. . . . . . . . . . . . . . . . . . . 4
1.4 SMB Gateway Application. . . . . . . . . . . . . . . . . . . . 5
1.5 WLAN Access Point Application . . . . . . . . . . . . . . . 5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Critical Performance Parameters . . . . . . . . . . . . . . 6
2.3 Chip-Level Features . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.1 e500v2 Cores and Memory Unit . . . . . . . . . 8
2.4.2 e500 Coherency Module (ECM) and Address
Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.3 Integrated Security Engine (SEC 3.3.2) . . . . 9
2.4.4 Enhanced Three-Speed Ethernet Controllers
(eTSECs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4.5 Universal Serial Bus (USB) 2.0 . . . . . . . . . 10
2.4.6 DDR SDRAM Controller. . . . . . . . . . . . . . . 11
2.4.7 High Speed I/O Interfaces . . . . . . . . . . . . . 12
2.4.8 Programmable Interrupt Controller (PIC) . . 12
2.4.9 Time Division Multiplexing (TDM) Interface 13
2.4.10 Enhanced Secure Digital Host Controller (eS-
DHC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.11 DMA, I
2
C, DUART, and Enhanced Local Bus
Controller (eLBC) . . . . . . . . . . . . . . . . . . . . 13
2.4.12 Device Boot Locations . . . . . . . . . . . . . . . . 14
2.4.13 System Performance Monitor. . . . . . . . . . . 14
Development Environment . . . . . . . . . . . . . . . . . . . . . . . 15
Document Revision History. . . . . . . . . . . . . . . . . . . . . . . 15
2
3
4
© Freescale Semiconductor, Inc., 2008. All rights reserved.
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