XRT7295AE
E3 (34.368Mbps)
Integrated line Receiver
March 2003
FEATURES
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APPLICATIONS
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Fully Integrated Receive Interface for E3
Signals
Integrated Equalization (Optional) and Timing
Recovery
Loss-of-Signal and Loss-of-Lock Alarms
Variable Input Sensitivity Control
5V Power Supply
Compliant with G703, G.775 and G.824 Specifi-
cations
Interface to E3 Networks
CSU/DSU Equipment
PCM Test Equipment
Fiber Optic Terminals
Multiplexers
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GENERAL DESCRIPTION
The XRT7295AE E3 Integrated Line Receiver is a fully
integrates receive interface that terminates a bipolar
E3 (34.3684 Mbps) signal transmitted over coaxial
Cable. This device can be used with the XRT7296
Integrated Line Transmitter (see Figure 10),
The device provides the functions of receive equaliza-
tion (optional) automatic gain control (AGC), clock
recovery and data re-timing, loss of signal and loss-of
frequency lock detection. The digital system interface
is a dual-rail with received positive and negative 1s
appearing as unipolar digital signals on separate output
leads. The on-chip equalizer is designed for cable
losses of 0 to 15dB. The receive input has a variable
input sensitivity control, providing three different sen-
sitivity settings. High input sensitivity allows for signifi-
cant amounts of flat loss or for use with input signals
at the monitor level. Figure 1 shows the block diagram
of the device.
The XRT7295AE is manufactured by using linear
CMOS technology. The XRT7295AE is available in a
20-pin plastic SOJ package for surface mounting. A pin
compatible version is available for DS3 or STS-1
applications. Please refer to the XRT7295AT data
sheet
ORDERING INFORMATION
Operating
Temperature Range
-40°C to +85°C
Part No.
XRT7295AEIW
Package
20 J-lead 300 MIL JEDEC SOJ
Rev. 2.0.0
EXAR
Corporation, 48720 Kato Road, Fremont, CA 94538
•
(510) 668-7000
•
FAX (510) 668-7017
XRT7295AE
Figure 1. Block Diagram
PIN CONFIGURATION
Rev. 2.0.0
2
XRT7295AE
PIN DESCRIPTION
Pin #
1
2
3,6
4,5
7
8
9
10
11
12
13
Symbol
GNDA
R
IN
TMC1-TMC2
LPF-1-LPF-2
RLOS
RLOL
GNDD
GNDC
V
DD
D
V
DD
C
EXCLK
I
I
I
I
O
O
Type
Description
Analog Ground.
Receive Input.
Unbalanced analog receive input
Test Mode Control 1 and 2.
Internal test modes are enabled within the device
by using TMC1 and TMC2. Users must tie these pins to the ground plane.
PLL Filter 1 and 2.
An external capacitor (0.1µF +/-20%) is connected
between these pins (See Figure 3).
Receive Loss-of-Signal.
This pin is set high on loss of signal at the receive
input.
Receive PLL Loss-of-Lock.
This pin is set high on loss of PLL frequency lock.
Digital Ground for PLL Lock.
Ground lead for all circuitry running
synchronously with PLL clock.
Digital Ground for EXCLK.
Ground lead for all circuitry running
synchronously with EXCLK.
5V Digital Supply (+/-10%) for PLL Clock.
Power for all circuitry running
synchronously with PLL clock.
5V Digital Supply (+/-10%) for EXCLK.
Power for all circuitry running
synchronously with EXCLK.
External Reference Clock.
A valid E3 (34.368MHz +/-100ppm) clock must be
provided at this input. The duty cycle of EXCLK, referenced to V
DD
/2 levels,
must be 40%-60%.
Receive Clock.
Recovered clock signal to the terminal equipment.
Receive Negative Data.
Negative pulse data output to the terminal
equipment.
Receive Positive Data.
Positive pulse data output to the terminal equipment.
Output In-Circuit Test Control (Active-Low).
If ICT is forced low, all digital
output pins (RCLK, RPDATA, RNDATA, RLOS, RLOL) are placed in a high-
impedance state to allow for in-circuit testing.
Receive Equalization Bypass.
A high on this pin bypasses the internal
equalizer. A low places the equalizer in the data path.
Loss-of-Signal Threshold Control.
The voltage forced on this pin controls the
input loss-of-signal threshold. Three settings are provided by forcing the GND,
V
DD
/2, or V
DD
at LOSTHR.
5V Analog Supply (+/-10%).
14
15
16
17
RCLK
RNDATA
RPDATA
ICT
O
O
O
I
18
19
REQB
LOSTHR
I
I
20
V
DD
A
Rev. 2.0.0
3
XRT7295AE
DC ELECTRICAL CHARACTERISTICS
Test Conditions: -40
°
C < TA < +85
°
C, VDD = 5V +/-10%
Typical values are for V
DD
=5.0V, 25
°
C, and random data. Maximum values for V
DD
= 5.5V at 85
°
C all
1s data.
Symbol Parameter
Electrical Characteristics
I
DD
Power Supply Current
REQB=0
REQB=1
82
79
106
103
mA
mA
Min.
Typ.
Max.
Unit
Conditions
Logical Interface Characteristics
V
IL
V
IH
Input Voltage
Low
High
Output Voltage
Low
High
Input Capacitance
Load Capacitance
Input Leakage
-10
GNDD
V
DD
D
-0.5
GNDD
V
DD
D
-0.5
0.5
V
DD
D
V
V
V
OL
V
OH
C
I
C
L
I
L
0.4
V
DD
D
10
10
10
V
V
pF
pF
µA
-5.0mA
5.0mA
0.02
10
-50
Note: Specifications are subject to change without notice.
0.5
100
-5
mA
µA
µA
-0.5 to V
DD
+0.5V (all
input pins except 2 and
17)
0V (pin 17)
V
DD
(pin 2)
GND (pin 2)
ABSOLUTE MAXIMUM RATINGS
Power Supply .......................
-0.5V to +6.5V
Storage Temperature ............
Voltage at any Pin ................
Power Dissipation .................
-40°C to +125°C
-0.5V to V
DD
+0.5V
700mW
Maximum Allowable Voltages (R
IN
)
with Respect to GND ..........
-0.5 to +5V
Rev. 2.0.0
4
XRT7295AE
XRT7295AE
XRT7296
XRT7296
Transmitter
XRT7295AE
Transmitter
Figure 2. Application Diagram
SYSTEM DESCRIPTION
Receive Path Configurations
The diagram in Figure 2 shows a typical system
application for the XRT7295AE. In the receive signal
path (see Figure 1), the internal equalizer can be
included by setting REQB=0 or bypass by setting
REQB=1. The equalizer bypass option allows easy
interfacing of the XRT7295AE into systems already
containing the external equalizers. Figure 3 illustrates
the receive path option for two separate cases.
In case 1, the signal from the coaxial cable feeds
directly into the R
IN
input. In this mode, the user should
set REQB=0, engaging the equalizer in the data path
if the cable loss is greater than 6dB. If the cable loss
is less than 6dB, the equalizer is bypassed by setting
the REQB=1.
In case 2, an external line and equalizer network
precedes the XRT7295AE. In this mode, the signal at
R
IN
is already equalized, and the on-chip equalizer
should be bypassed by setting REQB1=1. In both
cases, the signal at R
IN
must meet the amplitude limits
described in Table 1.
The recommended receive termination is also shown in
Figure 3. The 75Ω resistor terminates the coaxial cable
with its characteristic impedance. In Figure 3 case 2,
if the fixed equalizer includes the line termination, the
75Ω resistor is not required. The signal is AC coupled
through the 0.01µF capacitor to R
IN
. The DC bias at R
IN
is generated internally. The input capacitance at the
R
IN
pin is typically 2.8pF (SOJ package).
Pulse Mask at the 34.368 Mbps Interface
Table 2 shows the pulse specifications at the transmit-
ter output post and Figure 4 shows the pulse mask
requirement for E3 as recommended in G.703.
Minimum Signal
REQB
0
LOSTHR
0
V
DD
/2
V
DD
1
0
V
DD
/2
V
DD
NOTES:
1
2
3
Maximum input amplitude under all conditions is 1.1
Vpk.
The SOJ package performance is enhanced by de-
creased package parasitics.
Although system designers typically use power in dBm
to describe input levels, the XRT7295AE responds to
peak input signal amplitude. Therefore, the
XRT7295AE input signal limits are given in mV pk.
SOJ2
80
60
40
80
80
80
DIP
115
85
60
115
115
115
Unit3
mV pk
mV pk
mV pk
mV pk
mV pk
mV pk
Table 1. Receive Input Signal Amplitude
Requirements
Rev. 2.0.0
5
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