Table of Contents
Chapter 1. Introduction .......................................................................................................................... 3
Introduction ........................................................................................................................................................... 3
Quick Facts ........................................................................................................................................................... 3
Features ................................................................................................................................................................ 3
What Is Not Supported.......................................................................................................................................... 4
Conventions .......................................................................................................................................................... 4
Data Ordering and Data Types .................................................................................................................... 4
Signal Names............................................................................................................................................... 4
Chapter 2. Functional Description ........................................................................................................ 5
Rx Core ................................................................................................................................................................. 5
Tx Core ................................................................................................................................................................. 8
Interface Descriptions ......................................................................................................................................... 10
Chapter 3. Parameter Settings ............................................................................................................ 12
Parameters.......................................................................................................................................................... 12
Rx Core Parameter Selection ............................................................................................................................. 12
Tx Core Parameter Selection.............................................................................................................................. 13
Chapter 4. IP Core Generation............................................................................................................. 15
Licensing the IP Core.......................................................................................................................................... 15
Getting Started .................................................................................................................................................... 15
IPexpress-Created Files and Top Level Directory Structure............................................................................... 17
Instantiating the Core .......................................................................................................................................... 19
Running Functional Simulation ........................................................................................................................... 19
Simulation Strategies .......................................................................................................................................... 20
Simulation Environment ............................................................................................................................. 21
Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 21
Hardware Evaluation........................................................................................................................................... 22
Enabling Hardware Evaluation in Diamond................................................................................................ 22
Enabling Hardware Evaluation in ispLEVER.............................................................................................. 22
Updating/Regenerating the IP Core .................................................................................................................... 22
Regenerating an IP Core in Diamond ........................................................................................................ 22
Regenerating an IP Core in ispLEVER ...................................................................................................... 23
Chapter 5. Application Support........................................................................................................... 24
Chapter 6. Core Verification ................................................................................................................ 25
Chapter 7. Support Resources ............................................................................................................ 26
Lattice Technical Support.................................................................................................................................... 26
Online Forums............................................................................................................................................ 26
Telephone Support Hotline ........................................................................................................................ 26
E-mail Support ........................................................................................................................................... 26
Local Support ............................................................................................................................................. 26
Internet ....................................................................................................................................................... 26
References.......................................................................................................................................................... 26
Revision History .................................................................................................................................................. 27
Appendix A. Resource Utilization ....................................................................................................... 28
LatticeECP3-70 Utilization .................................................................................................................................. 28
Ordering Part Number................................................................................................................................ 28
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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JESD204A IP Core User’s Guide
Chapter 1:
Introduction
Introduction
JEDEC Standard No. 204A (JESD204A) describes a serialized interface between data converters and logic
devices. It contains the information necessary to allow designers to implement devices which can communicate
with other devices that are compliant with the standard. Lattice’s JESD204A IP Core offerings support both an Rx
core (ADC to FPGA direction) and/or a Tx core (FPGA to DAC direction). The Rx and Tx cores can each be gener-
ated separately and with different parameters.
Quick Facts
Table 1-1
gives quick facts about the JESD204A IP Cor for LatticeECP3™ devices.
Table 1-1. Quick Facts
JESD204A IP Configuration
2-lane configuration (F=3, L=2, K=9)
Core Requirements
FPGA Families Supported
Target Device
Data Path Width
Resources Utilization
LUTs
sysMEM™ EBRs
Registers
Lattice Implementation
Synthesis
Design Tool Support
Simulation
LatticeECP3
LFE3-70E
16 bits per lane, 32 bits total for 2 lanes
Rx: 1012 / Tx: 483
Rx: 0 / Tx: 0
Rx: 761 / Tx: 342
Lattice Diamond™ 1.1 or ispLEVER
®
8.1SP01
Synopsys
®
Synplify™ Pro for D-2010.03L-SP1
Aldec
®
Active-HDL™ 8.2 Lattice Edition
Mentor Graphics ModelSim™ SE 6.3F
Features
• Compliant with JEDEC Standard No. 204A (JESD204A) April 2008
• Rx core performs lane alignment buffering / detection / monitoring and correction
• Rx core performs frame alignment detection / monitoring and octet reconstruction
• Rx core performs user-enabled descrambling
• Rx core recovers link configuration parameters during initial lane synchronization and compares them to user-
selected parameters to generate a configuration mismatch error
• Tx core performs user-enabled scrambling
• Tx core generates initial lane alignment sequence
• Tx core performs alignment character generation
• Tx core sources link configuration data with user selected parameter values during initial lane synchronization
sequence
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JESD204A IP Core User’s Guide
Lattice Semiconductor
Introduction
What Is Not Supported
The core does not support the following features:
• Configuration of Rx core by link configuration parameters
• Octet to frame stream conversion in Rx core
• Frame to octet stream conversion in Tx core
• Verification of transport layer test samples within the Rx core
Conventions
The nomenclature used in this document is based on the Verilog language. This includes radix indications and log-
ical operators.
Data Ordering and Data Types
• The JESD204A IP core operates on individual bytes only, so there is no byte ordering defined for the core. How-
ever, to minimize the FPGA fabric clock frequency, the data path within the IP cores is two bytes wide. The byte
in the lower 8 bits of a 16-bit pair is the “low” byte, and the byte in the upper 8 bits is the “high” byte. On the inter-
face to user’s logic, each lane is a 16 bit interface. Within each 16-bit pair of bytes, the high byte is the first byte
transmitted or received, and the low byte is the second byte transmitted or received. On the interface between
the IP cores and the PCS/serdes, the low byte is the first byte of the pair, and the high byte is the second byte of
the pair.
• The most significant bit within data bytes is bit 7.
Signal Names
• Signal names that end with “_n” are active low.
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JESD204A IP Core User’s Guide
Chapter 2:
Functional Description
The JESD204A IP core implements the functionality described in the JEDEC standard. The following sections
describe the Rx and Tx cores.
Rx Core
Figure 2-1
shows the ports on the Rx IP core.
Figure 2-1. JESD204A Rx IP Core I/O
clk
reset_n
d_out_a[(L*16)-1:0]
Aligned user data
and octet count values
rx_ocnt_u_h[log2(F)-1:0]
rx_ocnt_u_l[log2(F)-1:0]
syncn
error/status
outputs
uncorr_align_err[L-1:0]
unexpect_ctrl[L-1:0]
frame_realigned[L-1:0]
cgs_err[L-1:0]]
cfg_mismatch_err[L-1:0]
init_align_fail
max_skew
all_aligned
lane_align[L-1:0]
ptr_offset[(L*4) -1:0]
fr_align_corr_en[L-1:0]
ln_align_corr_en[L-1:0]
scr_en[L-1:0]
JESD204A
Rx IP Core
rx_data[(L*16)-1:0]
rx_disp_err[(L*2)-1:0]
rx_cv_err[(L*2)-1:0]
rx_k[(L*2)-1:0]
from PCS/SERDES
Referring to
Figure 2-2,
in the Rx direction, serial I/F data is received by the logic device (FPGA) over one or more
serial I/F bit-stream lanes. The number of lanes is equal to the parameter L. The Rx core finds the framing informa-
tion for each lane and aligns all lanes to a common frame boundary. When the Rx core loses synchronization, it
sets the SYNC signal active which tells the Tx Block to send a new initialization sequence. Once the individual
lanes are aligned, the Rx core sources aligned sample stream data on its outputs to the user interface.
Figure 2-2. JESD204A Single Device Application
LatticeECP3 FPGA
Lane 0
Serial I/F Bit-Stream
JESD204A
RX Block
Sample
Stream (F)
Lane L-1
Serial I/F Bit-Stream
SYNC~ Signal
Frame Clock
Domain
Sample Clock
Domain
CLK
Gen
Frame Clock
JESD204A
TX Block
Sample
Stream F
Converter Device
Sample-to-Frame Rate
Sample
Stream (F)
Application
Logic
Sample
Stream F
Sample
Stream S
ADC 0
Conversion
Sample
Stream S
ADC
M-1
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JESD204A IP Core User’s Guide
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