DSP56367 24-Bit Digital Signal
Processor User’s Manual
Order Number: DSP56367UM/D
Revision 1.5, August 2003
© Motorola, Inc., 2003. All rights reserved.
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MOTOROLA INC. 2003
Rev. 1.5; published 08/03
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TABLE OF CONTENTS
Paragraph
Number
Page
Number
CHAPTER 1
DSP56367 OVERVIEW
1.1
1.2
1.3
1.4
1.4.1
1.4.1.1
1.4.1.2
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.4.9
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
Introduction ......................................................................................................................1-2
DSP56300 Core Description ...........................................................................................1-3
DSP56367 Audio Processor Architecture........................................................................1-4
DSP56300 Core Functional Blocks .................................................................................1-5
Data ALU ....................................................................................................................1-5
Data ALU Registers...............................................................................................1-5
Multiplier-Accumulator (MAC) ...............................................................................1-6
Address Generation Unit (AGU) .................................................................................1-6
Program Control Unit (PCU).......................................................................................1-6
Internal Buses ............................................................................................................1-7
Direct Memory Access (DMA) ....................................................................................1-8
PLL-based Clock Oscillator ........................................................................................1-8
JTAG TAP and OnCE Module....................................................................................1-8
On-Chip Memory ........................................................................................................1-9
Off-Chip Memory Expansion ......................................................................................1-9
Peripheral Overview ......................................................................................................1-10
Host Interface (HDI08)..............................................................................................1-10
General Purpose Input/Output (GPIO) .....................................................................1-11
Triple Timer (TEC)....................................................................................................1-11
Enhanced Serial Audio Interface (ESAI) ..................................................................1-11
Enhanced Serial Audio Interface 1 (ESAI_1) ...........................................................1-11
Serial Host Interface (SHI)........................................................................................1-12
Digital Audio Transmitter (DAX) ...............................................................................1-12
CHAPTER 2
SIGNAL / CONNECTION DESCRIPTIONS 1
2.1
2.1.1
2.2
2.3
2.4
2.5
2.5.1
2.5.2
2.5.3
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
Signal Groupings .............................................................................................................2-2
Power Requirements ..................................................................................................2-3
Power ..............................................................................................................................2-5
Ground.............................................................................................................................2-6
Clock and PLL .................................................................................................................2-7
External Memory Expansion Port (Port A).......................................................................2-7
External Address Bus .................................................................................................2-7
External Data Bus.......................................................................................................2-8
External Bus Control...................................................................................................2-8
Interrupt and Mode Control............................................................................................2-10
Parallel Host Interface (HDI08)......................................................................................2-12
Serial Host Interface ......................................................................................................2-18
Enhanced Serial Audio Interface ...................................................................................2-21
Enhanced Serial Audio Interface_1 ...............................................................................2-27
SPDIF Transmitter Digital Audio Interface ....................................................................2-30
Timer .............................................................................................................................2-31
JTAG/OnCE Interface....................................................................................................2-31
MOTOROLA
DSP56367 24-Bit Digital Signal Processor User’s Manual
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Number
CHAPTER 3
SPECIFICATIONS
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.10.1
3.10.2
3.10.3
3.11
3.12
3.13
3.13.1
3.14
3.15
3.16
3.17
3.18
Introduction ..................................................................................................................... 3-2
Maximum Ratings ........................................................................................................... 3-2
Thermal Characteristics .................................................................................................. 3-3
DC Electrical Characteristics .......................................................................................... 3-4
AC Electrical Characteristics........................................................................................... 3-5
Internal Clocks ................................................................................................................ 3-6
External Clock Operation ................................................................................................ 3-7
Phase Lock Loop (PLL) Characteristics.......................................................................... 3-8
Reset, Stop, Mode Select, and Interrupt Timing ............................................................. 3-9
External Memory Expansion Port (Port A) .................................................................... 3-16
SRAM Timing........................................................................................................... 3-16
DRAM Timing .......................................................................................................... 3-20
Arbitration Timings................................................................................................... 3-37
Parallel Host Interface (HDI08) Timing ......................................................................... 3-38
Serial Host Interface SPI Protocol Timing..................................................................... 3-46
Serial Host Interface (SHI) I
2
C Protocol Timing............................................................ 3-53
Programming the Serial Clock ................................................................................. 3-55
Enhanced Serial Audio Interface Timing....................................................................... 3-57
Digital Audio Transmitter Timing................................................................................... 3-62
Timer Timing ................................................................................................................. 3-63
GPIO Timing ................................................................................................................. 3-63
JTAG Timing ................................................................................................................. 3-65
CHAPTER 4
DESIGN CONSIDERATIONS
4.1
4.2
4.3
4.4
4.4.1
Thermal Design Considerations...................................................................................... 4-2
Electrical Design Considerations .................................................................................... 4-3
Power Consumption Considerations............................................................................... 4-4
PLL Performance Issues................................................................................................. 4-5
Input (EXTAL) Jitter Requirements............................................................................ 4-5
CHAPTER 5
MEMORY CONFIGURATION
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.2
Data and Program Memory Maps................................................................................... 5-2
Reserved Memory Spaces ...................................................................................... 5-13
Program ROM Area Reserved for Motorola Use ..................................................... 5-13
Bootstrap ROM ........................................................................................................ 5-13
Dynamic Memory Configuration Switching .............................................................. 5-13
External Memory Support ........................................................................................ 5-14
Internal I/O Memory Map .............................................................................................. 5-15
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DSP56367 24-Bit Digital Signal Processor User’s Manual
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CHAPTER 6
CORE CONFIGURATION
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.3
6.4
6.5
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.7
6.8
6.9
Introduction ......................................................................................................................6-2
Operating Mode Register (OMR).....................................................................................6-3
Asynchronous Bus Arbitration Enable (ABE) - Bit 13 .................................................6-3
Address Attribute Priority Disable (APD) - Bit 14........................................................6-3
Address Tracing Enable (ATE) - Bit 15 ......................................................................6-4
Patch Enable (PEN) - Bit 23 .......................................................................................6-4
Operating Modes .............................................................................................................6-6
Interrupt Priority Registers ...............................................................................................6-8
DMA Request Sources ..................................................................................................6-14
PLL Initialization ............................................................................................................6-15
PLL Multiplication Factor (MF0-MF11) .....................................................................6-15
PLL Pre-Divider Factor (PD0-PD3) ..........................................................................6-15
Crystal Range Bit (XTLR) .........................................................................................6-15
XTAL Disable Bit (XTLD)..........................................................................................6-15
Device Identification (ID) Register .................................................................................6-15
JTAG Identification (ID) Register ...................................................................................6-16
JTAG Boundary Scan Register (BSR)...........................................................................6-16
CHAPTER 7
GENERAL PURPOSE INPUT / OUTPUT
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
Introduction ......................................................................................................................7-2
Programming Model ........................................................................................................7-2
Port B Signals and Registers......................................................................................7-2
Port C Signals and Registers .....................................................................................7-2
Port D Signals and Registers .....................................................................................7-2
Port E Signals and Registers......................................................................................7-3
Timer/Event Counter Signals......................................................................................7-3
CHAPTER 8
HOST INTERFACE (HDI08)
8.1
8.2
8.2.1
8.2.2
8.3
8.4
8.5
8.5.1
8.5.2
8.5.3
8.5.3.1
8.5.3.2
8.5.3.3
8.5.3.4
8.5.3.5
Introduction ......................................................................................................................8-2
HDI08 Features ...............................................................................................................8-2
Interface - DSP side ...................................................................................................8-2
Interface - Host Side...................................................................................................8-3
HDI08 Host Port Signals..................................................................................................8-4
HDI08 Block Diagram ......................................................................................................8-5
HDI08 – DSP-Side Programmer’s Model ........................................................................8-7
Host Receive Data Register (HORX) .........................................................................8-7
Host Transmit Data Register (HOTX).........................................................................8-8
Host Control Register (HCR) ......................................................................................8-8
HCR Host Receive Interrupt Enable (HRIE) Bit 0 .................................................8-8
HCR Host Transmit Interrupt Enable (HTIE) Bit 1.................................................8-8
HCR Host Command Interrupt Enable (HCIE) Bit 2..............................................8-8
HCR Host Flags 2,3 (HF2,HF3) Bits 3-4 ...............................................................8-9
HCR Host DMA Mode Control Bits (HDM0, HDM1, HDM2) Bits 5-7 ....................8-9
MOTOROLA
DSP56367 24-Bit Digital Signal Processor User’s Manual
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