Power line chokes
Current-compensated ring core double chokes
250 V AC, 0.3 … 2 A, 1.1 … 22 mH, +40 °C
Series/Type:
Date:
B82720A/K
July 2012
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EPCOS
AG 2012. Reproduction, publication and dissemination of this publication, enclosures
hereto and the information contained therein without EPCOS’ prior express consent is prohibited.
Power line chokes
Current-compensated ring core double chokes
Rated voltage 250 V AC
Rated current 0.3 ... 2 A
Rated inductance 1.1 ... 22 mH
Construction
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■
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B82720A/K
Current-compensated ring core double choke
Ferrite core with epoxy coating (UL 94 V-0)
Polycarbonate case (UL 94 V-0)
Polyurethane potting (UL 94 V-0)
Sector winding
B82720A
Features
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High resonance frequency due to special winding technique
Approx. 0.7% stray inductance for symmetrical interference suppression
Suitable for wave soldering
Design complies with UL 1283 and EN 60938-2 (VDE 0565-2)
UL
1)
and ENEC (VDE) approvals
RoHS-compatible
B82720K
Applications
■
Suppression of common-mode interferences
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Compact electronic ballasts in lamps
■
Compact switch-mode power applications
Terminals
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Base material CuNi18Zn20
Layer composition Ni, Sn
Hot-dipped
Pins 0.5
0.5 (mm),
0.6 mm
Pins in the lead spacing 10
7.5 (mm) or 10
10 (mm)
Marking
■
Manufacturer, ordering code, rated inductance, rated current,
graphic symbol, rated voltage, date of manufacture (YYWWD)
Delivery mode
■
Cardboard box
1) UL approval with 300 V AC
Please read
Cautions and warnings
and
Important notes
at the end of this document.
2
07/12
Power line chokes
Current-compensated ring core double chokes
Dimensional drawings and pin configurations
Horizontal version (B82720A)
10±0.4
2±0.2
1
B82720A/K
Vertical version (B82720K)
13±0.3
10±0.2
1
2
4
3
7.6
_
0.3
3
2
14.2 max.
10±0.4
ø0.6
2
3
14.2 max.
4
9.6 max.
_
0.5
3
+0.2
7.5±0.2
9.5
_
0.4
+
4
14±0.3
1.5±0.1
1
2
4
3
IND0249-B
Tolerances to ISO 2768-M
unless otherwise noted.
Dimensions in mm.
Technical data and measuring conditions
Rated voltage V
R
Test voltage V
test
Rated temperature T
R
Rated current I
R
Rated inductance L
R
Inductance tolerance
Inductance decreaseL/L
0
Stray inductance L
stray,typ
DC resistance R
typ
Solderability (lead-free)
3.5
_
0.5
0.5
5±0.2
250 V AC (50/60 Hz)
1500 V AC, 2 s (line/line)
+40 °C
Referred to 50 Hz and rated temperature
Measured with Agilent 4284A at 10 kHz, 0.1 mA, +20 °C,
inductance is specified per winding.
–30/50% at +20 °C
<10% at DC magnetic bias with I
R
, +20 °C
Measured with Agilent 4284A at 10 kHz, 5 mA, +20 °C,
typical values
Measured at +20 °C, typical values, specified per winding
Sn96.5Ag3.0Cu0.5: +(245
5)
°C, (3
0.3)
s
Wetting of soldering area
95%
(to IEC 60068-2-20, test Ta)
+(260
5)
°C, (10
1)
s
(to IEC 60068-2-20, test Tb)
40/125/56 (to IEC 60068-1)
–25 °C … +40 °C,
75%
RH
Approx. 2.5 g
UL 1283, EN 60938-2
Resistance to soldering heat
(wave soldering)
Climatic category
Storage conditions (packaged)
Weight
Approvals
Please read
Cautions and warnings
and
Important notes
at the end of this document.
3
07/12
+
+
+
1
4
2
3
1
IND0250-9
Power line chokes
Current-compensated ring core double chokes
Characteristics and ordering codes
I
R
A
0.3
0.3
0.6
1.0
1.5
2.0
L
R
mH
22
12
4.4
3.0
1.6
1.1
L
stray,typ
H
130
80
30
20
10
6
R
typ
m
Ordering code
Horizontal version
Vertical version
B82720K2301N042
B82720K2301N040
B82720K2601N040
B82720K2102N040
B82720K2152N040
B82720K2202N040
B82720A/K
Approvals
1500 B82720A2301N042
1100 B82720A2301N040
400 B82720A2601N040
220 B82720A2102N040
110 B82720A2152N040
65 B82720A2202N040
= approval granted
Impedance |Z| versus frequency f
measured with windings in parallel at +20 °C,
typical values
10
6
IND0610-A
Current derating I
op
/I
R
versus ambient temperature T
A
Ω
| Z|
10
5
B82720
10
4
10
3
10
2 4
10
A/K2301N042
A/K2301N040
A/K2601N040
A/K2102N040
A/K2152N040
A/K2202N040
10
5
10
6
Hz 10
7
f
Please read
Cautions and warnings
and
Important notes
at the end of this document.
4
07/12
Cautions and warnings
Current-compensated ring core double chokes
■
Please note the recommendations in our Inductors data book (latest edition) and in the data
sheets.
– Particular attention should be paid to the derating curves given there. Derating must be applied
in case the ambient temperature in the application exceeds the rated temperature of the
component.
– Ensure the operation temperature (which is the sum of the ambient temperature and the
temperature rise caused by losses / self-heating) of the component in the application does not
exceed the maximum value specified in the climatic category.
– The soldering conditions should also be observed. Temperatures quoted in relation to wave
soldering refer to the pin, not the housing.
■
If the components are to be washed varnished it is necessary to check whether the washing
varnish agent that is used has a negative effect on the wire insulation, any plastics that are used,
or on glued joints. In particular, it is possible for washing varnish agent residues to have a
negative effect in the long-term on wire insulation.
Washing processes may damage the product due to the possible static or cyclic mechanical
loads (e.g. ultrasonic cleaning). They may cause cracks to develop on the product and its parts,
which might lead to reduced reliability or lifetime.
■
The following points must be observed if the components are potted in customer applications:
– Many potting materials shrink as they harden. They therefore exert a pressure on the plastic
housing or core. This pressure can have a deleterious effect on electrical properties, and in
extreme cases can damage the core or plastic housing mechanically.
– It is necessary to check whether the potting material used attacks or destroys the wire
insulation, plastics or glue.
– The effect of the potting material can change the high-frequency behaviour of the components.
■
Ferrites are sensitive to direct impact. This can cause the core material to flake, or lead to
breakage of the core.
■
Even for customer-specific products, conclusive validation of the component in the circuit can
only be carried out by the customer.
Please read
Cautions and warnings
and
Important notes
at the end of this document.
5
07/12