MITSUMI
System Reset PST70XX
System Reset
Monolithic IC PST70XX Series
Outline
These low reset type ICs function in a variety of CPU systems and other logic systems, to detect power
supply voltage and reset the system accurately when power is turned on or interrupted.
They are ideal for use in battery check circuits for products using batteries, as they have ultra-low current
consumption and a high precision voltage detection function.
Features
1.
2.
3.
4.
5.
6.
High precision voltage detection
Vs±2% max.
Ultra-low current consumption
I
CCH
=2µA typ. I
CCL
=3µA typ.
Low operating limit voltage
0.65V typ.
Hysteresis voltage provided in detection voltage
50mV typ.
Output current high for ON
30mA typ.
Detection voltage can be selected as desired within a range of 1.9V~4.6V
in 0.1V steps, as indicated below.
PST70XX
Detection voltage value
(Example: for 4.6V ....... PST7046)
Package
MMP-3A (PST70
TO-92A (PST70
M)
)
Applications
1.
2.
3.
4.
5.
Reset circuits in microcomputers, CPUs and MPUs.
Logic circuit reset circuits.
Battery voltage check circuits.
Back-up power supply switching circuits.
Level detection circuits.
Pin Assignment
1
2
3
V
CC
GND
V
OUT
1
3
1
2
V
CC
GND
V
OUT
2
3
1
2
3
TO-92A
MMP-3A
(TOP VIEW)
MITSUMI
System Reset PST70XX
Equivalent Circuit Diagram
Absolute Maximum Ratings
Item
Storage temperature
Operating temperature
Power supply voltage
Allowable loss
(Ta=25
°
C)
Symbol
T
STG
T
OPR
V
CC
max.
Pd
Rating
-40~+125
-20~+75
-0.3~+10
200 (MMP-3A)
300 (TO-92A)
Units
°
C
°
C
V
mW
Electrical Characteristics
Item
(Ta=25
°
C) (Except where noted otherwise, resistance unit is
Ω)
Symbol Measurement conditions Measurement circuit Min. Typ. Max. Units
4.6~
V
S
typ. 1.9 V
S
typ.
-2% (0.1V +2%
Step)
30
50
±0.01
0.2
0.4
0.1
3.0
2.0
5
10
30
70
0.65
8
5
30
6.0
4.0
30
30
70
150
0.85
100
Detection voltage
V
S
R
L
=470 V
CC
=H L
1
V
Hysteresis voltage
Detection voltage
temperature coefficient
Low-level output voltage
Output leakage current
Circuit current while on
V
S
V
S
/ T
V
OL
I
OH
I
CCL
I
CCH
t
PLH
t
PHL
V
OPL
I
OL
1
I
OL
2
R
L
=470 V
CC
=L
H
L
1
1
1
1
1
1
2
2
2
2
1
1
1
mV
%/
°
C
V
µA
µA
µA
µs
µs
V
mA
mA
R
L
=470 Ta=-20~+75
°
C
V
CC
=V
S
min. -0.05V
R
L
=470
V
CC
=10.0V
V
CC
=V
S
min. -0.05V
R
L
=∞
V
CC
=V
S
typ. /0.85V
R
L
=∞
R
L
=4.7k
C
L
=100pF
R
L
=4.7k
C
L
=100pF
7046~24
7023~19
7046~24
7023~19
Circuit current while off
"H"transport delay time
"L"transport delay time
Operation limit voltage
Output current while on 1
R
L
=4.7k V
OL
< 0.4V
=
V
CC
=V
S
min. -0.05V
R
L
=0
V
CC
=Vs min. -0.05V R
L
=0
Ta=-20
°
C~+75
°
C
Output current while on 2
FPGA/CPLD
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