PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS874004
PCI E
XPRESS
™
J
ITTER
A
TTENUATOR
G
ENERAL
D
ESCRIPTION
The ICS874004 is a high performance Differential-
to HCSL Jitter Attenuator designed for use in PCI
HiPerClockS™
Express™ systems. In some PCI Express™
systems, such as those found in desktop PCs, the
PCI Express™ clocks are generated from a low
bandwidth, highphase noise PLL frequency synthesizer. In these
systems, a jitter attenuator may be required to attenuate high
frequency random and deterministic jitter components from the
PLL synthesizer and from the system board. The ICS874004
has 3 PLL bandwidth modes: 200KHz, 400KHz, and 800KHz.
200KHz mode will provide maximum jitter attenuation, but with
higher PLL tracking skew and spread spectrum modulation from
the motherboard synthesizer may be attenuated. 400KHz
provides an intermediate bandwidth that can easily track
triangular spread profiles, while providing good jitter attenuation.
800KHz bandwidth provides the best tracking skew and will pass
most spread profiles, but the jitter attenuation will not be as good
as the lower bandwidth modes. Because some 2.5 Gb serdes
have x20 multipliers while others have than x25 multipliers, the
874004 can be set for 1:1 mode or 5/4 multiplication mode (i.e.
100MHz input/125MHz output) using the F_SEL pin.
Features
•
(4) Differential LVDS output pairs
•
(1) Differential clock input
•
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Output frequency range: 98MHz - 160MHz
•
Input frequency range: 98MHz - 128MHz
•
VCO range: 490MHz - 640MHz
•
Cycle-to-cycle jitter: 50ps (maximum) design target
•
3.3V operating supply
•
3 bandwidth modes allow the system designer to make jitter
attenuation/tracking skew design trade-offs
•
0°C to 70°C ambient operating temperature
ICS
The ICS874004 uses ICS 3
rd
Generation FemtoClock
TM
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express™ add-in cards.
PLL B
ANDWIDTH
BW_SEL
0 = PLL Bandwidth: ~200KHz
Float = PLL Bandwidth: ~400KHz (Default)
1 = PLL Bandwidth: ~800KHz
B
LOCK
D
IAGRAM
OEA
PU
P
IN
A
SSIGNMENT
QA0
nQA0
nQB0
QB0
V
DDO
FB_OUT
nFB_OUT
MR
BW_SEL
V
DDA
F_SEL
V
DD
OEA
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
QA0
V
DDO
QA1
nQA1
QB1
nQB1
nFB_IN
FB_IN
OEB
GND
nCLK
CLK
F_SEL PD
BW_SEL
0 = ~200KHz
Float = ~400KHz
1 = ~800KHz
Float
0 ÷5
(default)
1
÷4
nQA0
QA1
nQA1
CLK PD
nCLK PU
PD
FB_IN
nFB_IN PU
Phase
Detector
VCO
490-640MHz
QB0
nQB0
QB1
nQB1
ICS874004
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
÷5
FB_OUT
nFB_OUT
MR PD
OEB PU
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
874004AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 21, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS874004
PCI E
XPRESS
™
J
ITTER
A
TTENUATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 24
2, 3
4, 23
5
6
7
Name
nQA0, QA0
nQB0, QB0
V
DDO
FB_OUT
nFB_OUT
MR
Type
Output
Output
Power
Output
Output
Input
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Output supply pins.
Non-inver ting differential feedback output.
Inver ting differential feedback output.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (nQx) to go low and the inver ted outputs
Pulldown
(Qx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
Pullup/
Selects PLL Band Width input. LVCMOS/LVTTL interface levels.
Pulldown
Analog supply pin.
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Core supply pin.
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
Pullup
active. When LOW, the QAx/nQAx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Power supply ground.
Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are
Pullup
active. When LOW, the QBx/nQBx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
Pulldown Non-inver ting differential feedback input.
Pullup
Inver ting differential feedback input.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
8
9
10
11
12
13
14
15
16
17
18
19, 20
21, 22
BW_SEL
V
DDA
F_SEL
V
DD
OEA
CLK
nCLK
GND
OEB
FB_IN
nFB_IN
nQB1, QB1
nQA1, QA1
Input
Power
Input
Power
Input
Input
Input
Power
Input
Input
Input
Output
Output
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
T
ABLE
3A. O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
Inputs
OEA
0
1
OEB
0
1
QAx/nQAx
HiZ
Enabled
Outputs
QBx/nQBx
HiZ
Enabled
FB_OUT/nFB_OUT
Enabled
Enabled
T
ABLE
3B. PLL B
ANDWIDTH
/PLL B
YPASS
C
ONTROL
Inputs
BW_SEL
0
1
Float
PLL
Bandwidth
~200KHz
~800KHz
~400KHz
REV. A JANUARY 21, 2005
874004AG
www.icst.com/products/hiperclocks.html
2
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS874004
PCI E
XPRESS
™
J
ITTER
A
TTENUATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
70°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
60
8
82
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
Input High Voltage
F_SEL, MR,
OEA, OEB
BW_SEL
F_SEL, MR,
OEA, OEB
BW_SEL
BW_SEL, OEA, OEB
F_SEL, MR
BW_SEL, OEA, OEB
F_SEL, MR
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
Test Conditions
Minimum Typical
2
V
DD
- 0.3
-0.3
-0.3
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.3
5
150
Units
V
V
V
V
µA
µA
µA
µA
V
IL
I
IH
I
IL
Input Low Voltage
Input High Current
Input Low Current
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK, FB_IN
nCLK, nFB_IN
CLK, FB_IN
nCLK, nFB_IN
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
-150
0.15
1.3
5
150
Minimum
Typical
Maximum
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
V
DD
- 0.85
V
CMR
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK and FB_IN, nFB_IN is V
DD
+ 0.3V.
874004AG
www.icst.com/products/hiperclocks.html
3
REV. A JANUARY 21, 2005
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