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CAT24FC65JE-TE13

Description
LM5104 High Voltage Half-Bridge Gate Driver with Adaptive Delay; Package: SOIC NARROW; No of Pins: 8
Categorystorage    storage   
File Size446KB,10 Pages
ManufacturerCatalyst
Websitehttp://www.catalyst-semiconductor.com/
Download Datasheet Parametric View All

CAT24FC65JE-TE13 Overview

LM5104 High Voltage Half-Bridge Gate Driver with Adaptive Delay; Package: SOIC NARROW; No of Pins: 8

CAT24FC65JE-TE13 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerCatalyst
Parts packaging codeSOIC
package instructionSOP, SOP8,.25
Contacts8
Reach Compliance Codeunknow
ECCN codeEAR99
Maximum clock frequency (fCLK)1 MHz
Data retention time - minimum100
Durability1000000 Write/Erase Cycles
I2C control byte1010DDDR
JESD-30 codeR-PDSO-G8
JESD-609 codee0
length4.9 mm
memory density65536 bi
Memory IC TypeEEPROM
memory width8
Number of functions1
Number of terminals8
word count8192 words
character code8000
Operating modeSYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
organize8KX8
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP8,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialSERIAL
Peak Reflow Temperature (Celsius)240
power supply3/5 V
Certification statusNot Qualified
Maximum seat height1.75 mm
Serial bus typeI2C
Maximum standby current0.00001 A
Maximum slew rate0.003 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2.5 V
Nominal supply voltage (Vsup)3 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3.9 mm
Maximum write cycle time (tWC)5 ms
write protectHARDWARE
CAT24FC65, CAT24FC66
64K-Bit I
2
C Serial CMOS EEPROM with Partial Array Write Protection
FEATURES
I
Fast mode I
2
C bus compatible*
I
Max clock frequency:
I
5 ms max write cycle time
I
Write protect feature
- 400KHz for VCC=2.5V to 5.5V
I
Schmitt trigger filtered inputs for
noise suppression
I
Low power CMOS technology
I
64-byte page write buffer
I
Self-timed write cycle with auto-clear
I
Industrial and automotive temperature ranges
– Bottom 1/4 array protected when WP at V
IH
(CAT24FC65)
– Top 1/4 array protected when WP at V
IH
(CAT24FC66)
I
1,000,000 program/erase cycles
I
100 year data retention
I
8-pin DIP, 8-pin SOIC (JEDEC), 8-pin SOIC
(EIAJ), 8-pin TSSOP and TDFN packages
DESCRIPTION
The CAT24FC65/66 is a 64k-bit Serial CMOS EEPROM
internally organized as 8,192 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements.
The CAT24FC65/66 features a 64-byte page write
buffer. The device operates via the I
2
C bus serial
interface and is available in 8-pin DIP, SOIC, TSSOP
and TDFN packages.
PIN CONFIGURATION
DIP Package (P, L, GL)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
BLOCK DIAGRAM
EXTERNAL LOAD
DOUT
ACK
VCC
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
512
SDA
START/STOP
LOGIC
SENSE AMPS
SHIFT REGISTERS
A0
1
A1
2
A2
3
VSS
4
8
VCC
7
WP
6
SCL
5
SDA
TDFN Package (RD2, ZD2)
SOIC Package
(J, W, K, X, GW, GX)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
(Top View)
TSSOP Package (U, Y, GY)
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
WP
VCC
A0
WP
A1
SCL
A2
SDA
VSS
XDEC
CONTROL
LOGIC
128
EEPROM
128X512
PIN FUNCTIONS
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
NC
Function
Address Inputs
Serial Data/Address
Serial Clock
Write Protect
+2.5V to +5.5V Power Supply
Ground
No Connect
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
HIGH VOLTAGE/
TIMING CONTROL
DATA IN STORAGE
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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