HD6433877NX datasheet, PDF - EEWORLD Datasheet

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HD6433877NX: DescriptionMicrocontroller, 8-Bit, MROM, CMOS, PQFP100, TFP-100B; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，410 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

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HD6433877NX Overview

Microcontroller, 8-Bit, MROM, CMOS, PQFP100, TFP-100B

HD6433877NX Parametric

Parameter Name	Attribute value
Maker	Hitachi （Renesas ）
Parts packaging code	QFP
package instruction	TFQFP,
Contacts	100
Reach Compliance Code	unknown
Has ADC	YES
Address bus width
bit size	8
maximum clock frequency	10 MHz
DAC channel	NO
DMA channel	NO
External data bus width
JESD-30 code	S-PQFP-G100
length	14 mm
Number of I/O lines	80
Number of terminals	100
PWM channel	NO
Package body material	PLASTIC/EPOXY
encapsulated code	TFQFP
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE, FINE PITCH
Certification status	Not Qualified
ROM programmability	MROM
Maximum seat height	1.2 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	2.7 V
surface mount	YES
technology	CMOS
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER
Base Number Matches	1

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H8/3877N Series

H8/3877N, H8/3876N, H8/3875N

Hardware Manual

Contents

Section 1

1.1

1.2

1.3

Overview

..........................................................................................................

Overview.........................................................................................................................

Internal Block Diagram ..................................................................................................

Pin Arrangement and Functions .....................................................................................

1.3.1 Pin Arrangement.................................................................................................

1.3.2 Pin Functions ......................................................................................................

Section 2

2.1

CPU

................................................................................................................... 13

2.2

2.3

2.4

2.5

2.6

2.7

Overview.........................................................................................................................

2.1.1 Features...............................................................................................................

2.1.2 Address Space.....................................................................................................

2.1.3 Register Configuration........................................................................................

Register Descriptions......................................................................................................

2.2.1 General Registers................................................................................................

2.2.2 Control Registers ................................................................................................

2.2.3 Initial Register Values.........................................................................................

Data Formats...................................................................................................................

2.3.1 Data Formats in General Registers .....................................................................

2.3.2 Memory Data Formats ........................................................................................

Addressing Modes ..........................................................................................................

2.4.1 Addressing Modes ..............................................................................................

2.4.2 Effective Address Calculation ............................................................................

Instruction Set.................................................................................................................

2.5.1 Data Transfer Instructions ..................................................................................

2.5.2 Arithmetic Operations ........................................................................................

2.5.3 Logic Operations ................................................................................................

2.5.4 Shift Operations ..................................................................................................

2.5.5 Bit Manipulations ...............................................................................................

2.5.6 Branching Instructions........................................................................................

2.5.7 System Control Instructions ...............................................................................

2.5.8 Block Data Transfer Instruction .........................................................................

Basic Operational Timing ...............................................................................................

2.6.1 Access to On-Chip Memory (RAM, ROM) .......................................................

2.6.2 Access to On-Chip Peripheral Modules .............................................................

CPU States ......................................................................................................................

2.7.1 Overview.............................................................................................................

2.7.2 Program Execution State ...................................................................................

2.7.3 Program Halt State..............................................................................................

2.7.4 Exception-Handling State...................................................................................

2.8

2.9

Memory Map ..................................................................................................................

2.8.1 Memory Map ......................................................................................................

Application Notes ...........................................................................................................

2.9.1 Notes on Data Access .........................................................................................

2.9.2 Notes on Bit Manipulation..................................................................................

2.9.3 Notes on Use of the EEPMOV Instruction .........................................................

Section 3

3.1

3.2

Exception Handling

...................................................................................... 57

3.3

3.4

Overview.........................................................................................................................

Reset ............................................................................................................................

3.2.1 Overview.............................................................................................................

3.2.2 Reset Sequence ...................................................................................................

3.2.3 Interrupt Immediately after Reset.......................................................................

Interrupts.........................................................................................................................

3.3.1 Overview.............................................................................................................

3.3.2 Interrupt Control Registers .................................................................................

3.3.3 External Interrupts ..............................................................................................

3.3.4 Internal Interrupts ...............................................................................................

3.3.5 Interrupt Operations............................................................................................

3.3.6 Interrupt Response Time.....................................................................................

Application Notes ...........................................................................................................

3.4.1 Notes on Stack Area Use ....................................................................................

3.4.2 Notes on Rewriting Port Mode Registers ...........................................................

Section 4

4.1

Clock Pulse Generators

............................................................................... 81

4.2

4.3

4.4

4.5

Overview.........................................................................................................................

4.1.1 Block Diagram....................................................................................................

4.1.2 System Clock and Subclock ...............................................................................

System Clock Generator .................................................................................................

Subclock Generator ........................................................................................................

Prescalers ........................................................................................................................

Note on Oscillators .........................................................................................................

Section 5

5.1

5.2

Power-Down Modes

..................................................................................... 89

5.3

Overview.........................................................................................................................

5.1.1 System Control Registers ...................................................................................

Sleep Mode .....................................................................................................................

5.2.1 Transition to Sleep Mode....................................................................................

5.2.2 Clearing Sleep Mode ..........................................................................................

Standby Mode.................................................................................................................

5.3.1 Transition to Standby Mode ...............................................................................

5.4

5.5

5.6

5.7

5.8

5.3.2 Clearing Standby Mode ...................................................................................... 96

5.3.3 Oscillator Settling Time after Standby Mode is Cleared .................................... 97

Watch Mode.................................................................................................................... 98

5.4.1 Transition to Watch Mode .................................................................................. 98

5.4.2 Clearing Watch Mode ......................................................................................... 98

5.4.3 Oscillator Settling Time after Watch Mode is Cleared ....................................... 98

Subsleep Mode................................................................................................................ 99

5.5.1 Transition to Subsleep Mode .............................................................................. 99

5.5.2 Clearing Subsleep Mode..................................................................................... 99

Subactive Mode .............................................................................................................. 100

5.6.1 Transition to Subactive Mode ............................................................................. 100

5.6.2 Clearing Subactive Mode.................................................................................... 100

5.6.3 Operating Frequency in Subactive Mode ........................................................... 100

Active (medium-speed) Mode ........................................................................................ 101

5.7.1 Transition to Active (medium-speed) Mode....................................................... 101

5.7.2 Clearing Active (medium-speed) Mode ............................................................. 101

5.7.3 Operating Frequency in Active (medium-speed) Mode ..................................... 101

Direct Transfer ................................................................................................................ 102

Section 6

6.1

6.2

ROM

.................................................................................................................. 105

6.3

6.4

Overview......................................................................................................................... 105

6.1.1 Block Diagram ................................................................................................... 105

PROM Mode................................................................................................................... 106

6.2.1 Selection of PROM Mode .................................................................................. 106

6.2.2 Socket Adapter Pin Arrangement and Memory Map ......................................... 106

Programming .................................................................................................................. 109

6.3.1 Programming and Verification............................................................................ 110

6.3.2 Programming Precautions................................................................................... 114

Reliability of Programmed Data..................................................................................... 115

Section 7

7.1

RAM

................................................................................................................. 117

Overview......................................................................................................................... 117

7.1.1 Block Diagram ................................................................................................... 117

Section 8

I/O Ports

........................................................................................................... 119

8.1 Overview ............................................................................................................................ 119

8.2

Port 1 ............................................................................................................................ 121

8.2.1 Overview............................................................................................................. 121

8.2.2 Register Configuration and Description ............................................................. 121

8.2.3 Pin Functions ...................................................................................................... 125

8.2.4 Pin States ............................................................................................................ 126

HD6433877NX Related Products

	HD6433877NX	HD6433876NF	HD6473877NH	HD6433876NH	HD6433877NH	HD6433875NX	HD6433875NF	HD6433875NH	HD6433876NX	HD6433877NF
Description	Microcontroller, 8-Bit, MROM, CMOS, PQFP100, TFP-100B	Microcontroller, 8-Bit, MROM, CMOS, PQFP100, FP-100A	Microcontroller, 8-Bit, OTPROM, H8/300L CPU, 5MHz, CMOS, PQFP100, QFP-100	Microcontroller, 8-Bit, MROM, H8/300L CPU, 5MHz, CMOS, PQFP100, FP-100B	Microcontroller, 8-Bit, MROM, H8/300L CPU, 5MHz, CMOS, PQFP100, FP-100B	Microcontroller, 8-Bit, MROM, CMOS, PQFP100, TFP-100B	Microcontroller, 8-Bit, MROM, CMOS, PQFP100, FP-100A	Microcontroller, 8-Bit, MROM, H8/300L CPU, 5MHz, CMOS, PQFP100, FP-100B	Microcontroller, 8-Bit, MROM, CMOS, PQFP100, TFP-100B	Microcontroller, 8-Bit, MROM, CMOS, PQFP100, FP-100A
Parts packaging code	QFP	QFP	QFP	QFP	QFP	QFP	QFP	QFP	QFP	QFP
package instruction	TFQFP,	QFP,	FQFP, QFP100,.63SQ,20	FQFP, QFP100,.63SQ,20	FQFP, QFP100,.63SQ,20	TFQFP,	QFP,	FQFP, QFP100,.63SQ,20	TFQFP,	QFP,
Contacts	100	100	100	100	100	100	100	100	100	100
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
Has ADC	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
bit size	8	8	8	8	8	8	8	8	8	8
maximum clock frequency	10 MHz	10 MHz	10 MHz	10 MHz	10 MHz	10 MHz	10 MHz	10 MHz	10 MHz	10 MHz
DAC channel	NO	NO	NO	NO	NO	NO	NO	NO	NO	NO
DMA channel	NO	NO	NO	NO	NO	NO	NO	NO	NO	NO
JESD-30 code	S-PQFP-G100	R-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	R-PQFP-G100	S-PQFP-G100	S-PQFP-G100	R-PQFP-G100
length	14 mm	20 mm	14 mm	14 mm	14 mm	14 mm	20 mm	14 mm	14 mm	20 mm
Number of I/O lines	80	80	80	80	80	80	80	80	80	80
Number of terminals	100	100	100	100	100	100	100	100	100	100
PWM channel	NO	NO	NO	NO	NO	NO	NO	NO	NO	NO
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFQFP	QFP	FQFP	FQFP	FQFP	TFQFP	QFP	FQFP	TFQFP	QFP
Package shape	SQUARE	RECTANGULAR	SQUARE	SQUARE	SQUARE	SQUARE	RECTANGULAR	SQUARE	SQUARE	RECTANGULAR
Package form	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK	FLATPACK, FINE PITCH	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
ROM programmability	MROM	MROM	OTPROM	MROM	MROM	MROM	MROM	MROM	MROM	MROM
Maximum seat height	1.2 mm	3.1 mm	3.05 mm	3.05 mm	3.05 mm	1.2 mm	3.1 mm	3.05 mm	1.2 mm	3.1 mm
Maximum supply voltage	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	2.7 V	2.7 V	4 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.65 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.65 mm	0.5 mm	0.5 mm	0.65 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER
Maker	Hitachi （Renesas ）	Hitachi （Renesas ）	Hitachi （Renesas ）	-	Hitachi （Renesas ）	-	Hitachi （Renesas ）	Hitachi （Renesas ）	Hitachi （Renesas ）	Hitachi （Renesas ）
Base Number Matches	1	1	1	1	1	1	-	-	-	-

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