HS-565ARH-T
TM
Data Sheet
November 2000
File Number
4607.2
Radiation Hardened High Speed,
Monolithic Digital-to-Analog Converter
Intersil’s Satellite Applications Flow
TM
(SAF) devices are fully
tested and guaranteed to 100 krad total dose. This QML
Class T device is processed to a standard flow intended to
meet the cost and shorter lead-time needs of large volume
satellite manufacturers, while maintaining a high level of
reliability.
The HS-565ARH-T is a fast, radiation hardened 12-bit
current output, digital-to-analog converter. The monolithic
chip includes a precision voltage reference, thin-film R-2R
ladder, reference control amplifier and twelve high-speed
bipolar current switches.
The Intersil Semiconductor Dielectric Isolation process
provides latch-up free operation while minimizing stray
capacitance and leakage currents, to produce an excellent
combination of speed and accuracy. Also, ground currents
are minimized to produce a low and constant current through
the ground terminal, which reduces error due to code-
dependent ground currents.
HS-565ARH-T die are laser trimmed for a maximum integral
nonlinearity error of
±0.25
LSB at 25
o
C. In addition, the low
noise buried zener reference is trimmed both for absolute value
and minimum temperature coefficient.
Features
• qml Class T, Per MIL-PRF-38535
• Radiation Performance
- Gamma Dose (γ) 1 x 10
5
Rad (Si)
- No Latch-Up, Dielectrically Isolated Device Islands
• DAC and Reference on a Single Chip
• Pin Compatible with AD-565A and HI-565A
• Very High Speed: Settles to 0.50 LSB in 500ns Max
• Monotonicity Guaranteed Over Temperature
• 0.50 LSB Max Nonlinearity Guaranteed Over Temperature
• Low Gain Drift (Max., DAC Plus Reference) 50ppm/
o
C
•
±0.75
LSB Accuracy Guaranteed Over Temperature
(±0.125 LSB Typical at 25
o
C)
Pinouts
HS1-565ARH-T (SBDIP), CDIP2-T24
TOP VIEW
NC 1
NC 2
V
CC
3
REF OUT 4
REF GND 5
REF IN 6
-V
EE
7
BIPOLAR RIN 8
IDAC OUT 9
10V SPAN 10
20V SPAN 11
PWR GND 12
24 BIT 1 IN (MSB)
23 BIT 2 IN
22 BIT 3 IN
21 BIT 4 IN
20 BIT 5 IN
19 BIT 6 IN
18 BIT 7 IN
17 BIT 8 IN
16 BIT 9 IN
15 BIT 10 IN
14 BIT 11 IN
13 BIT 12 IN (LSB)
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HS-565ARH-T
are contained in SMD 5962-96755.
A “hot-link” is provided
from our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Intersil‘s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
HS9-565ARH-T (FLATPACK), CDFP4-F24
TOP VIEW
NC
NC
V
CC
REF OUT
REF GND
REF IN
-V
EE
BIPOLAR RIN
IDAC OUT
10V SPAN
20V SPAN
PWR GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
BIT 1 IN
(MSB)
BIT 2 IN
BIT 3 IN
BIT 4 IN
BIT 5 IN
BIT 6 IN
BIT 7 IN
BIT 8 IN
BIT 9 IN
BIT 10 IN
BIT 11 IN
BIT 12 IN
(LSB)
Ordering Information
ORDERING
NUMBER
5962R9675501TJC
5962R9675501TXC
PART
NUMBER
HS1-565ARH-T
HS9-565ARH-T
TEMP.
RANGE
(
o
C)
-55 to 125
-55 to 125
NOTE:
Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright © Intersil Corporation 2000
HS-565ARH-T
Functional Diagram
REF OUT V
CC
4
3
+
BIP.
OFF.
8
5K
10V
I
REF
0.5mA
3.5K
3K
7
-V
EE
12
PWR
GND
+
DAC
IO
(4X IREF
X CODE)
2.5K
9.95K
5K
10 10V
SPAN
9
OUT
11 20V
SPAN
-
REF
IN
6 19.95K
REF 5
GND
-
24. . . 13
MSB LSB
Definitions of Specifications
Digital Inputs
The HS-565ARH-T accepts digital input codes in binary
format and may be user connected for any one of three
binary codes. Straight binary, Two’s Complement (see note
below), or Offset Binary (see Operating Instructions).
DIGITAL
INPUT
MSB . LSB
000 . . . 000
100 . . . 000
111 . . . 111
011 . . . 111
STRAIGHT
BINARY
Zero
0.50 f
S
+ f
S
- 1 LSB
0.50 f
S
- 1 LSB
ANALOG OUTPUT
OFFSET
BINARY
- f
S
(Full Scale)
Zero
+ f
S
- 1 LSB
Zero - 1 LSB
(NOTE)
TWO’S
COMPLEMENT
Zero
- f
S
Zero - 1 LSB
+ f
S
- 1 LSB
full scale range per
o
C (ppm of FSR/
o
C). Gain error is
measured with respect to 25
o
C at high (t
H
) and low (t
L
)
temperatures. Gain drift is calculated for both high (t
L
-
25
o
C) and low ranges (25
o
C - t
L
) by dividing the gain error
by the respective change in temperature. The specification is
the larger of the two representing worst case drift.
Offset Drift -
The change in analog output with all bits OFF
over the specified temperature range expressed in parts per
million of full scale range per
o
C (ppm of FSR/
o
C). Offset
error is measured with respect to 25
o
C at high (t
H
) and low
(t
L
) temperatures. Offset drift is calculated for both high (t
D
-
25
o
C) and low (25
o
C - t
L
) ranges by dividing the offset error
by the respective change in temperature. The specification
given is the larger of the two, representing worst case drift.
Power Supply Sensitivity
Power Supply Sensitivity is a measure of the change in
gain and offset of the D/A converter resulting from a
change in -15V or +15V supplies. It is specified under DC
conditions and expressed as parts per million of full scale
range per percent of change in power supply (ppm of
FSR/%).
NOTE: Invert MSB with external inverter to obtain Two’s
Complement Coding.
Accuracy
Nonlinearity -
Nonlinearity of a D/A converter is an
important measure of its accuracy. It describes the deviation
from an ideal straight line transfer curve drawn between zero
(all bits OFF) and full scale (all bits ON).
Differential Nonlinearity -
For a D/A converter, it is the
difference between the actual output voltage change and the
ideal (1 LSB) voltage change for a one bit change in code. A
Differential Nonlinearity of
±1
LSB or less guarantees
monotonicity; i.e., the output always increases and never
decreases for an increasing input.
Compliance
Compliance Voltage is the maximum output voltage range
that can be tolerated and still maintain its specified accuracy.
Compliance Limit implies functional operation only and
makes no claims to accuracy.
Glitch
A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times.
Worst case glitches usually occur at half scale or the major
carry code transition from 011 . . . 1 to 100 . . . 0 or vice
versa. For example, if turn ON is greater than turn OFF for
011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0
exists, such that, the output momentarily glitches toward
zero output. Matched switching times and fast switching will
reduce glitches considerably.
Settling Time
Settling time is the time required for the output to settle to
within the specified error band for any input code transition.
It is usually specified for a full scale or major carry transition,
settling to within 0.50 LSB of final value.
Drift
Gain Drift -
The change in full scale analog output over the
specified temperature range expressed in parts per million of
2
HS-565ARH-T
Applying the HS-565ARH-T
OP AMP Selection
The HS-565ARH-T’s current output may be converted to
voltage using the standard connections shown in Figures 1
and 2. The choice of operational amplifier should be
reviewed for each application, since a significant trade-off
may be made between speed and accuracy. Remember
settling time for the DAC-amplifier combination
is:
(
t
D
)
2
+
(
t
A
)
2
No Trim Operation
The HS-565ARH-T will perform as specified without
calibration adjustments. To operate without calibration,
substitute 50Ω resistors for the 100Ω trimming
potentiometers: In Figure 1 replace R2 with 50Ω; also
remove the network on pin 8 and connect 50Ω to ground.
For bipolar operation in Figure 2, replace R3 and R4 with
50Ω resistors.
With these changes, performance is guaranteed as shown
under Specifications, “External Adjustments”. Typical
unipolar zero will be
±0.50
LSB plus the op amp offset.
The feedback capacitor C must be selected to minimize
settling time.
+15V
R1
50kΩ
-15V
where t
D
, t
A
are settling times for the DAC and amplifier.
100kΩ
R2
100Ω
100Ω
REF OUT V
CC
4
3
BIP.
OFF.
HS-565ARH-T
+
8
11
20V SPAN
5K
10
10V SPAN V
O
DAC
OUT
9
2.5K
-
6
REF
IN
REF
GND
5
19.95
K
10V
I
REF
0.5mA
3.5K
3K
CODE
INPUT
7
-V
EE
PWR
GND
24 . . . . .13
MSB
LSB
+
9.95K
DAC
IO
(4 x I
REF
x CODE)
5K
-
C
-
+
R (SEE
TABLE 7)
FIGURE 1. UNIPOLAR VOLTAGE OUTPUT
R4
100Ω
REF OUT
V
CC
4
3
R3
100Ω
BIP.
OFF.
8
11
20V SPAN
5K
10
10V SPAN V
O
DAC
OUT
9
2.5K
HS-565ARH-T
+
-
6
REF
IN 5
REF
GND
19.95K
10V
I
REF
0.5mA
3.5K
3K
CODE
INPUT
7
-V
EE
24 . . . . .13
MSB
LSB
+
9.95K
DAC
IO
(4 x I
REF
x CODE)
5K
-
C
-
+
R (SEE
TABLE 7)
PWR
GND
FIGURE 2. BIPOLAR VOLTAGE OUTPUT
3
HS-565ARH-T
Calibration
Calibration provides the maximum accuracy from a
converter by adjusting its gain and offset errors to zero, For
the HS-565ARH-T, these adjustments are similar whether
the current output is used, or whether an external op amp is
added to convert this current to a voltage. Refer to Table 7
for the voltage output case, along with Figure 1 or 2.
Calibration is a two step process for each of the five output
ranges shown in Table 1. First adjust the negative full scale
(zero for unipolar ranges). This is an offset adjust which
translates the output characteristic, i.e., affects each code by
the same amount.
Next adjust positive f
S
. This is a gain error adjustment, which
rotates the output characteristic about the negative f
S
value.
For the bipolar ranges, this approach leaves an error at the
zero code, whose maximum values is the same as for
integral nonlinearity error. In general, only two values of
output may be calibrated exactly; all others must tolerate
some error. Choosing the extreme end points (plus and
minus full scale) minimizes this distributed error for all other
codes.
shown this to be a reliable and repeatable way to measure
settling time.
The usual specification is based on a 10V step, produced by
simultaneously switching all bits from off-to-on (t
ON
) or on-
to-off (t
OFF
). The slower of the two cases is specified, as
measured from 50% of the digital input transition to the final
entry within a window of
±0.50
LSB about the settled value.
Four measurements characterize a given type of DAC:
(a) t
ON
, to final value +0.50 LSB
(b) t
ON
, to final value -0.50 LSB
(c) t
OFF
, to final value +0.50 LSB
(d) OFF, to final value -0.50 LSB
(Cases (b) and (c) may be eliminated unless the overshoot
exceeds 0.50 LSB). For example, refer to Figures 3A and 3B
for the measurement of case (d).
Procedure
As shown in Figure 3B, settling time equals t
X
plus the
comparator delay (t
D
= 15ns). To measure t
X
:
• Adjust the delay on generator number 2 for a t
X
of several
microseconds. This assures that the DAC output has
settled to its final wave
• Switch on the LSB (+5V)
• Adjust the VLSB supply for 50% triggering at
COMPARATOR OUT. This is indicated by traces of equal
brightness on the oscilloscope display as shown in Figure
3B. Note DVM reading
• Switch to LSB to Pulse (P)
• Readjust the VLSB supply for 50% triggering as before,
and note DVM reading. One LSB equals one tenth the
difference in the DVM readings noted above
• Adjust the VLSB supply to reduce the DVM reading by 5
LSBs (DVM reads 10X, so this sets the comparator to
sense the final settled value minus 0.50 LSB). Comparator
output disappears
• Reduce generator number 2 delay until comparator output
reappears, and adjust for “equal brightness”
• Measure t
X
from scope as shown in Figure 3B. Settling
time equals t
X
+ t
D
, i.e., t
X
+ 15ns
CALIBRATION
RESISTOR
(R)
1.43K
1.1K
APPLY
INPUT CODE
All 0’s
All 1’s
All 0’s
All 1’s
ADJUST
R1
R2
R1
R2
TO SET VO
0V
+9.99756V
0V
+4.99878V
Settling Time
This is a challenging measurement, in which the result
depends on the method chosen, the precision and quality of
test equipment and the operating configuration of the DAC
(test conditions). As a result, the different techniques in use
by converter manufacturers can lead to consistently different
results. An engineer should understand the advantage and
limitations of a given test method before using the specified
settling time as a basis for design.
The approach used for several years at Intersil calls for a
strobed comparator to sense final perturbations of the DAC
output waveform. This gives the LSB a reasonable
magnitude (814mV for the HS-565ARH-T, which provides
the comparator with enough overdrive to establish an
accurate
±0.50
LSB window about the final settled value.
Also, the required test conditions simulate the DACs
environment for a common application - use in a successive
approximation A/D converter. Considerable experience has
TABLE 1. OPERATING MODES AND CALIBRATION
CIRCUIT CONNECTIONS
MODE
Unipolar (See Figure 1)
OUTPUT
RANGE
0 to +10V
0 to +5V
PIN 10
TO
VO
VO
PIN 11
TO
Pin 10
Pin 9
4
HS-565ARH-T
TABLE 1. OPERATING MODES AND CALIBRATION (Continued)
CIRCUIT CONNECTIONS
MODE
Bipolar (See Figure 2)
OUTPUT
RANGE
±10V
±5V
±2.5V
PIN 10
TO
NC
VO
VO
PIN 11
TO
VO
Pin 10
Pin 9
RESISTOR
(R)
1.69K
1.43K
1.1K
APPLY
INPUT CODE
All 0’s
All 1’s
All 0’s
All 1’s
All 0’s
All 1’s
CALIBRATION
ADJUST
R3
R4
R3
R4
R3
R4
TO SET VO
-10V
+9.99512V
-5V
+4.99756V
-2.5V
+2.49878V
OUT
A
SYNC
PULSE
PULSE
OUT
IN
GENERATOR
TRIG
GENERATOR
OUT
NO. 2
NO. 2
C
20V
±
20%
BIAS
HS-565ARH-T
24
8
11
5K
10
5K
9
B
+
-
2.5K
5
12
DVM
90
10
200K
0.1µF
VLSB
SUPPLY
D
23
.
.
.
. 9.95K
.
.
.
.
.
.
~100 .
kHz .
.
14
P 13 2mA
5V
LSB
TURN ON
TURN OFF
+3V
NC
STROBE IN
D
COMPARATOR
OUT
B
A
50%
0V
-0.50LSB
0V
DIGITAL
INPUT
DAC
OUTPUT
SETTLING TIME
tD = COMPARATOR DELAY
-400mV
(TURN OFF)
2V
C
t
X
50%
COMP.
STROBE
“EQUAL BRIGHTNESS”
COMP.
OUT
0.8V
4V
0V
FIGURE 3A.
FIGURE 3B.
the main and auxiliary ladders draw a continuous 2.25mA from the
internal ground node, regardless of input code. Part of the DC current
is supplied by the zener voltage reference, and the remainder is
sourced from the positive supply via a current mirror which is laser
trimmed for zero current through the external terminal (pin 5).
Other Considerations
Grounds
The HS-565ARH-T has two ground terminals, pin 5 (REF
GND) and pin 12 (PWR GND). These should not be tied
together near the package unless that point is also the
system signal ground to which all returns are connected. (If
such a point exists, then separate paths are required to pins
5 and 12).
The current through pin 5 is near zero DC (Note); but pin 12
carries up to 1.75mA of code - dependent current from bits
1, 2, and 3. The general rule is to connect pin 5 directly to
the system “quiet” point, usually called signal or analog
ground. Connect pin 12 to the local digital or power ground.
Then, of course, a single path must connect the
analog/signal and digital/power grounds.
NOTE: Current cancellation is a two step process within the HS-
565ARH-T in which code dependent variations are eliminated, the re-
sulting DC current is supplied internally. First an auxiliary 9-bit R-2R
ladder is driven by the complement of the DACs input code. Together,
Layout
Connections to pin 9 (I
OUT
) on the HS-565ARH-T are most
critical for high speed performance. Output capacitance of
the DAC is only 20pF, so a small change of additional
capacitance may alter the op amp’s stability and affect
settling time. Connections to pin 9 should be short and few.
Component leads should be short on the side connecting to
pin 9 (as for feedback capacitor C). See the Settling Time
Section.
Bypass Capacitors
Power supply bypass capacitors on the op amp will serve the
HS-565ARH-T also. If no op amp is used, a 0.01mF ceramic
capacitor from each supply terminal to pin 12 is sufficient,
since supply current variations are small.
5
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