XC6116A239 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > XC6116A239

Preview

XC6116A239: DescriptionCMOS Voltage Detector; File Size519KB，26 Pages; Manufacturer

Download Datasheet View All

XC6116A239 Overview

CMOS Voltage Detector

Preview

Download Datasheet

View All

Preliminary

◆CMOS

Voltage Detector

◆Manual

Reset Input

◆Watchdog

Functions

◆Built-in

Delay Circuit

◆Detect

Voltage Range: 1.6~5.0V, ± 2%

◆Reset

Function is Selectable

DFL

(Low When Detected)

DFH

(High When Detected)

■APPLICATIONS

●Microprocessor

reset circuits

●Memory

battery backup circuits

●System

power-on reset circuits

●Power

failure detection

■GENERAL

DESCRIPTION

■FEATURES

Detect Voltage Range

Hysteresis Range

: 1.6V ~ 5.0V, +2%

(100mV increments)

: V

x 5%, TYP.

(XC6101~XC6107)

x 0.1%, TYP.

(XC6111~XC6117)

: 1.0V ~ 6.0V

The XC6101~XC6107, XC6111~XC6117 series are

groups of high-precision, low current consumption voltage

detectors with manual reset input function and watchdog

functions incorporating CMOS process technology. The

series consist of a reference voltage source, delay circuit,

comparator, and output driver.

With the built-in delay circuit, the XC6101 ~ XC6107,

XC6111 ~ XC6117 series’ ICs do not require any external

components to output signals with release delay time.

Moreover, with the manual reset function, reset can be

asserted at any time. The ICs produce two types of

output; V

DFL

(low when detected) and V

DFH

(high when

detected).

With the XC6101 ~ XC6105, XC6111 ~ XC6115 series’

ICs, the WD pin can be left open if the watchdog function

is not used.

Whenever the watchdog pin is opened, the internal

counter clears before the watchdog timeout occurs.

Since the manual reset pin is internally pulled up to the V

pin voltage level, the ICs can be used with the manual

reset pin left unconnected if the pin is unused.

The detect voltages are internally fixed 1.6V ~ 5.0V in

increments of 100mV, using laser trimming technology.

Six watchdog timeout period settings are available in a

range from 6.25msec to 1.6sec.

Seven release delay time 1 are available in a range from

3.13msec to 1.6sec.

Operating Voltage Range

Detect Voltage Temperature

Characteristics

: +100ppm/

C (TYP.)

Output Configuration

: N-channel open drain,

CMOS

Watchdog Pin

: Watchdog input

If watchdog input maintains

‘H’ or ‘L’ within the watchdog

timeout period, a reset signal

is output to the RESET

output pin

Manual Reset Pin

: When driven ‘H’ to ‘L’ level

signal, the MRB pin voltage

asserts forced reset on the

output pin.

Release Delay Time

: 1.6sec, 400msec, 200msec,

100msec, 50msec, 25msec,

3.13msec (TYP.) can be

selectable.

Watchdog Timeout Period

: 1.6sec, 400msec, 200msec,

100msec, 50msec,

6.25msec (TYP.) can be

selectable.

■TYPICAL

APPLICATION CIRCUIT

■TYPICAL

PERFORMANCE

CHARACTERISTICS

●Supply

Current vs. Input Voltage

XC61X1~XC61X5 (2.7V)

Supply Current:

ISS (µA)

Input Voltage:

VIN (V)

Ta=-40

℃

Ta=25

℃

Ta=85

℃

* Not necessary with CMOS output products.

* ‘x’ represents both ‘0’ and ‘1’. (ex. XC61x1⇒XC6101 and XC6111)

XC6101_07_XC6111_17 ETR0207_009

1/26

Recommended Resources

Long delay constant current charging circuit

Ultrasonic insect repellent circuit 02

Typical application circuit diagram with regulation function

High-precision regulated power supply circuit diagram

Overload power control circuit

ring timing generator

Use PCA/PWM module to adjust PWM phase: When PCA is in high-speed output mode (outputting PWM wave), the output flips when a set comparison value is reached, and no interrupt is made. Then, when the match occurs, does the value of the compa...; kbj305 Embedded System

FPGA-specific terminology glossary.pdf: FPGA-specific terminology glossary.pdf:):):)...; 白丁 FPGA/CPLD

"FPGA Three Kingdoms" (XI) Part 2 - Structure: Altera FPGA is not as fast as Xilinx, wrong! Of course, you must have a certain understanding of this asymmetric structure to make better use of it. That is to say, you must follow: large data through...; liumnqti FPGA/CPLD

F3-FCYF2 network interface circuit diagram: F3-FCYF2 network interface circuit diagram...; klanlan Industrial Control Electronics

Share 2018 Electronics Competition Paper - [B- Fire Extinguishing Aircraft] Fujian Province Ti Cup Special Prize / Xiamen University / Changmen University Team: [i=s]This post was last edited by Jacktang on 2021-8-5 10:39[/i]SummaryThe quadcopter is a small-sized, relatively simple-to-control aircraft. The quadcopter designed in this project uses only a TI MS...; Jacktang Electronics Design Contest

It's my turn to interview a newcomer. Let me share my thoughts.: I have worked diligently in the company for more than a year. Now it is finally my turn to interview new people. Let me share my thoughts. We have recruited several engineering assistants. 1) Academic...; cl17726 Talking

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components