Part Number 405EXr
Revision 1.09 - May 2, 2008
405EXr
PowerPC 405EXr Embedded Processor
Features
• AMCC PowerPC
®
405 32-bit RISC processor core
operating from 333MHz to 533MHz including
16KB I- and D-caches with parity checking
• On-chip 128-bit processor local bus (PLB)
operating up to 200MHz
• On-chip 32-bit peripheral bus (OPB) operating up
to 100 MHz
• External 8-,16-, or 32-bit peripheral bus (EBC)
operating up to 100MHz
• External bus master (EBM) operating up to
100MHz
• On-chip Security feature with True Random
Number generation
• Eight- and 16-bit NAND Flash interface
• Inter-chip connectivity (SCP and IIC)
• Boot from NOR Flash on the external peripheral
bus or NAND Flash on the NAND Flash interface
• DMA (4-channel) support for all on-chip slaves
and external bus, UARTs, and devices on the EBC
• DDR1/2 SDRAM interface operating up to 400
Mbps
Preliminary Data Sheet
• One one-lane PCI Express interfaces operating up
to 2.5 Gbps
• One Gigabit Ethernet interfaces (half- and full-
duplex) to external PHY (GMII/MII/RGMII)
• USB 2.0 OTG port configurable as either Host or
Device
• Programmable universal interrupt controller (UIC)
• General Purpose Timer (GPT)
• Up to two serial ports (16750 compatible UART)
• Two IIC interfaces operating up to 400kHz and
supporting all standard IIC EEPROMs
• One SCP (SPI) synchronous full-duplex channel
operating up to 25 MHz
• General purpose I/Os (GPIOs), each with
programmable interrupts and outputs
• Supports JTAG for board-level testing
• System power management, low power
dissipation and small form factor
• Available in a RoHS compliant (lead-free) package
Description
With speeds up to 533MHz, a flexible off-chip memory
architecture, and a diverse communications package
that includes PCI Express, USB 2.0 OTG, and
10/100/1000 Ethernet, the PowerPC 405EXr
embedded processor provides a low power and small
footprint system-on-a-chip (SOC) solution for a wide
range of high performance, cost-constrained
embedded applications. This includes wireless LAN
applications, security appliances, internet appliances,
line cards, and intelligent USB peripherals. It is an
easily programmable general purpose, 32-bit RISC
controller that offers an upgrade path for applications
in need of performance and connectivity
improvements.
Technology: Cu-08 CMOS, 90nm
Package: 388-ball, 27mm
×
27mm, enhanced plastic
ball grid array (EPBGA), 1mm ball pitch
Power consumption (est.): less than 1.5W, typical
Voltages required: 3.3V, 2.5V, 1.8V (DDR2 SDRAM
only), and 1.2V
AMCC Proprietary
1
PPC405EXr – PowerPC 405EXr Embedded Processor
Revision 1.09 - May 2, 2008
Preliminary Data Sheet
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PowerPC 405 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
USB 2.0 OTG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DDR1/2 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Security Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Serial Communication Port Interface (SCP/SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General Purpose I/O (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Signal Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Ratings and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
DDR 2/1 SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PCI Express (PCI-E) I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2
AMCC Proprietary
PPC405EXr – PowerPC 405EXr Embedded Processor
Revision 1.09 - May 2, 2008
Preliminary Data Sheet
List of Figures
Figure 1.
PPC405EXr Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2.
Package 27mm, 388-Ball EPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3.
Clocking Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 4.
Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 5.
Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 6.
Input Setup and Hold Timing Waveform for RGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 7.
Output Delay and Hold Timing Waveform for RGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 8.
DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 9.
DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 10.
DDR SDRAM Read Data Path for a Single Data Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 11.
DDR SDRAM Memory Data and DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 12.
DDR SDRAM Read Cycle Timing—Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
AMCC Proprietary
3
PPC405EXr – PowerPC 405EXr Embedded Processor
Revision 1.09 - May 2, 2008
Preliminary Data Sheet
List of Tables
Table 1.
System Memory Address Map (4GB System Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2.
DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3.
Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4.
Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 5.
Pin Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 6.
Non-Functional Ball Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 7.
Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 8.
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 9.
Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 10.
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 11.
I/O Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 12.
Typical DC Power Supply Requirements with DDR1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 13.
Typical DC Power Supply Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 14.
DC Power Supply Loads with DDR1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 15.
DC Power Supply Loads with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 16.
System Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 17.
Peripheral Interface I/O Clock Timings (not SDRAM or PCI-E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 18.
I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 19.
DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 20.
DDR SDRAM Write Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 21.
I/O Timing—DDR SDRAM T
DS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 22.
I/O Timing—DDR SDRAM T
SA
and T
HA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 23.
I/O Timing—DDR SDRAM Write Timing T
SD
and T
HD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 24.
I/O Timing—DDR SDRAM Read Timing T
SD
and T
HD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 25.
PCI-E Receiver I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 26.
PCI-E Reference Clock I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 27.
PCI-E Transmitter I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 28.
Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4
AMCC Proprietary
PPC405EXr – PowerPC 405EXr Embedded Processor
Revision 1.09 - May 2, 2008
Preliminary Data Sheet
Ordering, PVR, and JTAG Information
This section provides the part number nomenclature. For availability, contact your local AMCC sales office.
Order Part Number
(see Notes:)
PPC405EXr-SpBfffT
PPC405EXr-NpBfffT
Rev
Level
A
A
Product Name
PPC405EXr
PPC405EXr
Notes:
1.
2.
3.
4.
Package
27mm, 388-ball, EPBGA
27mm, 388-ball, EPBGA
PVR Value
0x12911473
0x12911471
JTAG ID
0x1405B1E1
0x1405B1E1
S = security feature present, N = security feature not present
p = Package: S = lead-free (RoHS compliant), P = leaded
B = Chip revision level A
fff = Processor frequency
333 = 333MHz
400 = 400MHz
533 = 533MHz
5. T = Case temperature range, -40°C to +85°C
The part number contains a part modifier. Included in the modifier is a revision code. This refers to the die mask
revision number and is specified in the part numbering scheme for identification purposes only.
The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain
information that uniquely identifies the part. See the
PPC405EXr Embedded Processor User’s Manual
for details
about accessing these registers.
Order Part Number Key
PPC405EXr-SSB533T
AMCC Part Number
Case Temperature Range
Processor Speed (MHz)
Security
Chip Package
Revision Level
Note:
The example P/N above has the security feature, is lead-free, capable of running at 533MHz,
and is shipped in a tray (tape-and-reel packaging is not available).
AMCC Proprietary
5
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