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DS150 (v2.4) January 19, 2012
Product Specification
www.xilinx.com
1
Virtex-6 Family Overview
Virtex-6 FPGA Feature Summary
Table 1:
Virtex-6 FPGA Feature Summary by Device
Configurable Logic
Blocks (CLBs)
Device
Logic
Cells
Slices
(1)
Max
Distributed
RAM (Kb)
DSP48E1
Slices
(2)
Block RAM Blocks
18 Kb
(3)
36 Kb
Max
(Kb)
Interface
MMCMs
(4)
Blocks for Ethernet
(5)
PCI Express MACs
Maximum
Transceivers
GTX
GTH
Total
I/O
Banks
(6)
Max
User
I/O
(7)
XC6VLX75T
74,496
11,640
20,000
31,200
37,680
56,880
85,920
1,045
1,740
3,040
3,650
4,130
6,200
8,280
5,090
7,640
3,040
3,050
4,570
6,370
288
480
640
768
576
864
864
1,344
2,016
576
576
864
864
312
528
688
832
832
1,264
1,440
1,408
156
264
344
416
416
632
720
704
5,616
9,504
12,384
14,976
14,976
22,752
25,920
25,344
6
10
10
12
12
18
18
12
18
12
12
18
18
1
2
2
2
2
2
0
2
2
4
2
4
4
4
4
4
4
4
4
0
4
4
4
2
4
4
12
20
20
24
24
36
0
24
36
48
24
48
48
0
0
0
0
0
0
0
0
0
0
24
24
24
9
15
15
18
18
30
30
18
21
8
12
18
18
360
600
600
720
720
1200
1200
720
840
320
480
720
720
XC6VLX130T 128,000
XC6VLX195T 199,680
XC6VLX240T 241,152
XC6VLX365T 364,032
XC6VLX550T 549,888
XC6VLX760
758,784 118,560
49,200
74,400
39,360
39,600
59,760
88,560
XC6VSX315T 314,880
XC6VSX475T 476,160
XC6VHX250T 251,904
XC6VHX255T 253,440
XC6VHX380T 382,464
XC6VHX565T 566,784
2,128 1,064 38,304
1,008
1,032
1,536
1,824
504
516
768
912
18,144
18,576
27,648
32,832
Notes:
1.
2.
3.
4.
5.
6.
7.
Each Virtex-6 FPGA slice contains four LUTs and eight flip-flops, only some slices can use their LUTs as distributed RAM or SRLs.
Each DSP48E1 slice contains a 25 x 18 multiplier, an adder, and an accumulator.
Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18 Kb blocks.
Each CMT contains two mixed-mode clock managers (MMCM).
This table lists individual Ethernet MACs per device.
Does not include configuration Bank 0.
This number does not include GTX or GTH transceivers.
DS150 (v2.4) January 19, 2012
Product Specification
www.xilinx.com
2
Virtex-6 Family Overview
Virtex-6 FPGA Device-Package Combinations and Maximum I/Os
Virtex-6 LXT and SXT FPGA package combinations with the maximum available I/Os per package are shown in
Table 2.
Table 2:
Virtex-6 LXT and SXT FPGA Device-Package Combinations and Maximum Available I/Os
Package
Size (mm)
Device
XC6VLX75T
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
XC6VSX315T
XC6VSX475T
Notes:
1.
Flip-chip packages are also available in Pb-Free versions (FFG).
FF484
FFG484
23 x 23
GTXs
8
8
FF784
FFG784
29 x 29
FF1156
FFG1156
35 x 35
FF1759
FFG1759
42.5 x 42.5
FF1760
FFG1760
42.5 x 42.5
GTXs
I/O
I/O
240
240
GTXs
12
12
12
12
I/O
360
400
400
400
GTXs
I/O
GTXs
I/O
20
20
20
20
600
600
600
600
24
24
36
720
720
840
0
0
1200
1200
20
20
600
600
24
36
720
840
Virtex-6 HXT FPGA package combinations with the maximum available I/Os per package are shown in
Table 3.
Table 3:
Virtex-6 HXT FPGA Device-Package Combinations and Maximum Available I/Os
Package
Size (mm)
Device
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
Notes:
1.
Flip-chip packages are also available in Pb-Free versions (FFG).
FF1154
FFG1154
35 x 35
GTXs
48
FF1155
FFG1155
35 x 35
I/O
320
24
12
12
440
440
24
40
40
FF1923
FFG1923
45 x 45
I/O
GTXs
GTHs
I/O
GTXs
FF1924
FFG1924
45 x 45
GTHs
I/O
GTHs
0
GTXs
GTHs
24
24
24
480
720
720
48
48
24
24
640
640
48
0
320
24
DS150 (v2.4) January 19, 2012
Product Specification
www.xilinx.com
3
Virtex-6 Family Overview
Configuration
Virtex-6 FPGAs store their customized configuration in SRAM-type internal latches. The number of configuration bits is
between 26 Mb and 177 Mb, depending on device size but independent of the specific user-design implementation, unless
compression mode is used. The configuration storage is volatile and must be reloaded whenever the FPGA is powered up.
This storage can also be reloaded at any time by pulling the PROGRAM_B pin Low. Several methods and data formats for
loading configuration are available, determined by the three mode pins.
Bit-serial configurations can be either master serial mode where the FPGA generates the configuration clock (CCLK) signal,
or slave serial mode where the external configuration data source also clocks the FPGA. For byte- and word-wide
configurations, master SelectMAP mode generates the CCLK signal while slave SelectMAP mode receives the CCLK signal
for the 8-, 16-, or 32-bit-wide transfer. Alternatively, serial-peripheral interface (SPI) and byte-peripheral interface (BPI)
modes are used with industry-standard flash memories and are clocked by the CCLK output of the FPGA. JTAG mode uses
boundary-scan protocols to load bit-serial configuration data.
The bitstream configuration information is generated by the ISE® software using a program called BitGen. The configuration
process typically executes the following sequence:
•
•
•
•
•
Detects power-up (power-on reset) or PROGRAM_B when Low.
Clears the whole configuration memory.
Samples the mode pins to determine the configuration mode: master or slave, bit-serial or parallel, or bus width.
Loads the configuration data starting with the bus-width detection pattern followed by a synchronization word, checks
for the proper device code, and ends with a cyclic redundancy check (CRC) of the complete bitstream.
Start-up executes a user-defined sequence of events: releasing the internal reset (or preset) of flip-flops, optionally
waiting for the phase-locked loops (PLLs) to lock and/or the DCI to match, activating the output drivers, and transitions
the DONE pin High.
Dynamic Reconfiguration Port
The dynamic reconfiguration port (DRP) gives the system designer easy access to configuration bits and status registers for
three block types: 32 locations for each clock tile, 128 locations for the System Monitor, and 128 locations for each serial
GTX or GTH transceiver.
The DRP behaves like memory-mapped registers, and can access and modify block-specific configuration bits as well as
status and control registers.
Encryption, Readback, and Partial Reconfiguration
As a special option, the bitstream can be AES-encrypted to prevent unauthorized copying of the design. The Virtex-6 FPGA
performs the decryption using the internally stored 256-bit key that can use battery backup or alternative non-volatile
storage.
Most configuration data can be read back without affecting the system’s operation. Typically, configuration is an all-or-
nothing operation, but the Virtex-6 FPGA also supports partial reconfiguration. When applicable in certain designs, partial
reconfiguration can greatly improve the versatility of the FPGA. It is even possible to reconfigure a portion of the FPGA while
the rest of the logic remains active i.e., active partial reconfiguration.
CLBs, Slices, and LUTs
The look-up tables (LUTs) in Virtex-6 FPGAs can be configured as either one 6-input LUT (64-bit ROMs) with one output, or
as two 5-input LUTs (32-bit ROMs) with separate outputs but common addresses or logic inputs. Each LUT output can
optionally be registered in a flip-flop. Four such LUTs and their eight flip-flops as well as multiplexers and arithmetic carry
logic form a slice, and two slices form a configurable logic block (CLB). Four flip-flops per slice (one per LUT) can optionally
be configured as latches. In that case, the remaining four flip-flops in that slice must remain unused.
Between 25–50% of all slices can also use their LUTs as distributed 64-bit RAM or as 32-bit shift registers (SRL32) or as two
SRL16s. Modern synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features. Expert
designers can also instantiate them.
DS150 (v2.4) January 19, 2012
Product Specification
www.xilinx.com
4
Virtex-6 Family Overview
Clock Management
Each Virtex-6 FPGA has up to nine clock management tiles (CMTs), each consisting of two mixed-mode clock managers
(MMCMs), which are PLL based.
Phase-Locked Loop
The MMCM can serve as a frequency synthesizer for a wider range of frequencies and as a jitter filter for incoming clocks.
The heart of the MMCM is a voltage-controlled oscillator (VCO) with a frequency from 600 MHz up to 1600 MHz, spanning
more than one octave. There are three sets of programmable frequency dividers (D, M, and O).
The pre-divider D (programmable by configuration) reduces the input frequency and feeds one input of the traditional PLL
phase/frequency comparator. The feedback divider (programmable by configuration) acts as a multiplier because it divides
the VCO output frequency before feeding the other input of the phase comparator. D and M must be chosen appropriately
to keep the VCO within its specified frequency range.
The VCO has eight equally-spaced output phases (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to
drive one of the seven output dividers, O0 to O6 (each programmable by configuration to divide by any integer from 1 to 128).
MMCM Programmable Features
The MMCM has three input-jitter filter options: low bandwidth, high bandwidth, or optimized mode. Low-bandwidth mode has
the best jitter attenuation but not the smallest phase offset. High-bandwidth mode has the best phase offset, but not the best
jitter attenuation. Optimized mode allows the tools to find the best setting.
The MMCM can have a fractional counter in either the feedback path (acting as a multiplier) or in one output path. Fractional
counters allow non-integer increments of 1/8 and can thus increase frequency synthesis capabilities by a factor of 8.
The MMCM can also provide fixed or dynamic phase shift in small increments that depend on the VCO frequency. At
600 MHz the phase-shift timing increment is 30 ps; at 1600 MHz, it is 11.5 ps.
Clock Distribution
Each Virtex-6 FPGA provides five different types of clock lines (BUFG, BUFR, BUFIO, BUFH, and the high-performance
clock) to address the different clocking requirements of high fanout, short propagation delay, and extremely low skew.
Global Clock Lines
In each Virtex-6 FPGA, 32 global-clock lines have the highest fanout and can reach every flip-flop clock, clock enable,
set/reset, as well as many logic inputs. There are 12 global clock lines within any region. Global clock lines can be driven by
global clock buffers, which can also perform glitchless clock multiplexing and the clock enable function. Global clocks are
often driven from the CMT, which can completely eliminate the basic clock distribution delay.
Regional Clocks
Regional clocks can drive all clock destinations in their region as well as the region above and below. A region is defined as
any area that is 40 I/O and 40 CLB high and half the chip wide. Virtex-6 FPGAs have between 6 and 18 regions. There are
6 regional clock tracks in every region. Each regional clock buffer can be driven from either of four clock-capable input pins,
and its frequency can optionally be divided by any integer from 1 to 8.
I/O Clocks
I/O clocks are especially fast and serve only I/O logic and serializer/deserializer (SerDes) circuits, as described in the
I/O
Logic
section. Virtex-6 devices have a high-performance direct connection from the MMCM to the I/O directly for low-jitter,
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