5962-9560013Q9X datasheet, PDF

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5962-9560013Q9X: DescriptionStandard SRAM, 512KX8, 15ns, CMOS, FP-32; Categorystorage storage; File Size1MB，41 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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5962-9560013Q9X Overview

Standard SRAM, 512KX8, 15ns, CMOS, FP-32

5962-9560013Q9X Parametric

Parameter Name	Attribute value
Objectid	1198216771
Parts packaging code	DFP
package instruction	DFP,
Contacts	32
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	15 ns
JESD-30 code	R-XDFP-F32
length	21.01 mm
memory density	4194304 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	512KX8
Package body material	UNSPECIFIED
encapsulated code	DFP
Package shape	RECTANGULAR
Package form	FLATPACK
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	3.3 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
width	11.1633 mm

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REVISIONS

LTR

DESCRIPTION

Change minimum dimensions A, b, and E for case outline U. Add

CAGE 65786 as a source of supply. Editorial changes throughout. -

ksr

Change case outline 9, dimension A from .114 inches to .130 inches. -

glg

Added low-power devices 09 - 14 to drawing. Removed CAGE

0EU86 for devices 05 - 08. - glg

Changed minimum dimension b for package "U" from 0.015 inches to

0.012 inches. - glg

Changed minimum dimension b for package "M" from 0.019 inches to

0.012 inches. Updated boilerplate paragraphs. ksr

Table I; Changed the I

from 8 mA to 6 mA V

test. Added device

types 15 and 16. Editorial changes throughout. -sld

Add case outline 7. Add CAGE 0EU86 as source of supply for case

outline 7. Editorial changes throughout. tcr

Add device 17 and add case outline 6. Add CAGE 6S055 as source

of supply for case outline 6. Some editorial changes. ksr

Update drawing to meet current MIL-PRF-38535 requirements. - glg

DATE

97-10-24

APPROVED

Raymond Monnin

00-03-01

00-11-22

00-12-13

02-02-12

04-05-25

08-08-18

09-01-22

16-09-01

Raymond Monnin

Robert M. Heber

Charles Saffle

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Jeff Bowling

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

http://www.landandmaritime.dla.mil/

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS

AVAILABLE

FOR USE BY All

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

AMSC N/A

CHECKED BY

Jeff Bowling

APPROVED BY

Michael. A. Frye

DRAWING APPROVAL DATE

96-03-05

REVISION LEVEL

MICROCIRCUITS, MEMORY, DIGITAL,

CMOS, 512K X 8 STATIC RANDOM

ACCESS MEMORY (SRAM),

MONOLITHIC SILICON

SIZE

SHEET

1 OF

5962-E505-16

CAGE CODE

67268

5962-95600

DSCC FORM 2233

APR 97

2. APPLICABLE DOCUMENTS

2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part

of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the

solicitation or contract.

DEPARTMENT OF DEFENSE SPECIFICATION

MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

DEPARTMENT OF DEFENSE STANDARDS

MIL-STD-883 -

MIL-STD-1835 -

Test Method Standard Microcircuits.

Interface Standard Electronic Component Case Outlines.

DEPARTMENT OF DEFENSE HANDBOOKS

MIL-HDBK-103 -

MIL-HDBK-780 -

List of Standard Microcircuit Drawings.

Standard Microcircuit Drawings.

(Copies of these documents are available online at

http://quicksearch.dla.mil

or from the Standardization Document Order

Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.

Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation.

JEDEC –

SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)

JESD 78

IC Latch-Up Test.

(Copies of these documents

are available online at

http://www.jedec.org

or from JEDEC – Solid State Technology

Association, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107.)

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text

of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-

38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in

the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device cla ss M

shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.

3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

3.2.3 Truth table. The truth table shall be as specified on figure 3.

3.2.4 Functional tests. Various functional tests used to test this device are contained in the appendix. If the test patterns

cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be

allowed. For device class M, alternate test patterns shall be maintained under document revision level control by the

manufacturer and shall be made available to the preparing or acquiring activity upon request. For device classes Q and V

alternate test patterns shall be under the control of the device manufacturer's Technology Review Board (TRB) in accordance

with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request.

STANDARD

MICROCIRCUIT DRAWING

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

SIZE

REVISION LEVEL

5962-95600

SHEET

DSCC FORM 2234

APR 97

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full

case operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical

tests for each subgroup are defined in table I.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be

in accordance with MIL-PRF-38535, appendix A.

3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in

MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of

compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see

6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of

supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-

PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in

MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to

this drawing.

3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime-VA of change of

product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.

3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritime's agent,

and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Of fshore

documentation shall be made available onshore at the option of the reviewer.

3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in

microcircuit group number 41 (see MIL-PRF-38535, appendix A).

4. VERIFICATION

4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with

MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan

shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in

accordance with MIL-PRF-38535, appendix A.

4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted

on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in

accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.

4.2.1 Additional criteria for device class M.

a. Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in) electrical

parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.

b. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made

available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases,

and power dissipation, as applicable, in accordance with the intent specified in method 1015.

(1) Dynamic burn-in (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein).

c. Interim and final electrical parameters shall be as specified in table IIA herein.

STANDARD

MICROCIRCUIT DRAWING

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

SIZE

REVISION LEVEL

5962-95600

SHEET

DSCC FORM 2234

APR 97

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