5962-9851301QXB datasheet, PDF

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5962-9851301QXB: DescriptionField Programmable Gate Array, 576 CLBs, 10000 Gates, 166MHz, CMOS, CPGA223, PGA-223; CategoryProgrammable logic devices Programmable logic; File Size170KB，22 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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5962-9851301QXB Overview

Field Programmable Gate Array, 576 CLBs, 10000 Gates, 166MHz, CMOS, CPGA223, PGA-223

5962-9851301QXB Parametric

Parameter Name	Attribute value
Objectid	1528377536
Parts packaging code	PGA
package instruction	PGA,
Contacts	223
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
maximum clock frequency	166 MHz
Combined latency of CLB-Max	1.6 ns
JESD-30 code	S-CPGA-P223
JESD-609 code	e0
length	47.244 mm
Configurable number of logic blocks	576
Equivalent number of gates	10000
Number of terminals	223
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	576 CLBS, 10000 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class Q
Maximum seat height	4.318 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	47.244 mm

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QPRO XQ4000XL Series QML

High-Reliability FPGAs

DS029 (v1.3) June 25, 2000

Product Specification

•

Development system runs on most common computer

platforms

- Interfaces to popular design environments

- Fully automatic mapping, placement and routing

- Interactive design editor for design optimization

Highest capacity—over 180,000 usable gates

Additional routing over XQ4000E

- Almost twice the routing capacity for high-density

designs

Buffered Interconnect for maximum speed

New latch capability in configurable logic blocks

Improved VersaRing™ I/O interconnect for better Fixed

pinout flexibility

- Virtually unlimited number of clock signals

Optional multiplexer or 2-input function generator on

device outputs

5V tolerant I/Os

0.35

µm

SRAM process

XQ4000X Series Features

•

Certified to MIL-PRF-38535 Appendix A QML

(Qualified Manufacturer Listing)

Ceramic and plastic packages

Also available under the following standard microcircuit

drawings (SMD)

- XQ4013XL 5962-98513

- XQ4036XL 5962-98510

- XQ4062XL 5962-98511

- XQ4085XL 5962-99575

For more information contact the Defense Supply

Center Columbus (DSCC)

http://www.dscc.dla.mis/v/va/smd/smdsrch.html

Available in -3 speed

System featured Field-Programmable Gate Arrays

- SelectRAM™ memory: on-chip ultra-fast RAM with

synchronous write option

dual-port RAM option

- Abundant flip-flops

- Flexible function generators

- Dedicated high-speed carry logic

- Wide edge decoders on each edge

- Hierarchy of interconnect lines

- Internal 3-state bus capability

- Eight global low-skew clock or signal distribution

networks

•

Introduction

The QPRO™ XQ4000XL Series high-performance,

high-capacity Field Programmable Gate Arrays (FPGAs)

provide the benefits of custom CMOS VLSI, while avoiding

the initial cost, long development cycle, and inherent risk of

a conventional masked gate array.

The result of thirteen years of FPGA design experience and

feedback from thousands of customers, these FPGAs com-

bine architectural versatility, on-chip Select-RAM memory

with edge-triggered and dual-port modes, increased speed,

abundant routing resources, and new, sophisticated

soft-ware to achieve fully automated implementation of

complex, high-density, high-performance designs.

Refer to the complete Commercial XC4000XL Series Field

Programmable Gate Arrays Data Sheet for more informa-

tion on device architecture and timing, and the latest Xilinx

databook for package pinouts other than the CB228

(included in this data sheet). (Pinouts for XQ4000XL device

are identical to XC4000XL.)

•

System performance beyond 50 MHz

Flexible array architecture

Low power segmented routing architecture

Systems-oriented features

- IEEE 1149.1-compatible boundary scan logic

support

•

- Individually programmable output slew rate

- Programmable input pull-up or pull-down resistors

- 12 mA sink current per XQ4000XL output

Configured by loading binary file

- Unlimited reprogrammability

Readback capability

- Program verification

- Internal node observability

http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS029 (v1.3) June 25, 2000

Product Specification

www.xilinx.com

1-800-255-7778

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