a
FEATURES
Improved Version of AD7545
Fast Interface Timing
All Grades 12-Bit Accurate
20-Lead DIP and Surface Mount Packages
Low Cost
CMOS 12-Bit
Buffered Multiplying DAC
AD7545A
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7545A, a 12-bit CMOS multiplying DAC with internal
data latches, is an improved version of the industry standard
AD7545. This new design features a
WR
pulse width of 100 ns,
which allows interfacing to a much wider range of fast 8-bit and
16-bit microprocessors. It is loaded by a single 12-bit-wide word
under the control of the
CS
and
WR
inputs; tying these control
inputs low makes the input latches transparent, allowing unbuf-
fered operation of the DAC.
PIN CONFIGURATIONS
DIP/SOIC
LCCC
PLCC
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD7545A–SPECIFICATIONS
(V
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Temperature Coefficient
2
∆Gain/∆Temperature
DC Supply Rejection
2
∆Gain/∆V
DD
Output Leakage Current at OUT1
Version
All
K, B, T
L, C, U
All
K, B, T
L, C, U
All
All
All
K, L
B, C
T, U
All
12
±
1/2
±
1/2
±
1
±
3
±
1
±
5
±
2
0.002
10
10
10
1
12
±
1/2
±
1/2
±
1
±
4
±
2
±
5
±
2
REF
=
10 V, V
OUT1
= O V, AGND = DGND unless otherwise noted)
V
DD
= +15 V
Limits
T
A
= + 25 C T
MIN
–T
MAX1
12
±
1/2
±
1/2
±
1
±
3
±
1
±
5
±
2
0.002
10
10
10
1
12
±
1/2
±
1/2
±
1
±
4
±
2
±
5
±
2
0.004
50
50
200
1
V
DD
= +5 V
Limits
T
A
= + 25 C T
MIN
–T
MAX1
Units
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
ppm/°C max
ppm/°C typ
% per % max
nA max
nA max
nA max
µs
max
Test Conditions/Comments
Endpoint Measurement
All Grades Guaranteed 12-Bit
Monotonic Over Temperature
Measured Using Internal R
FB
.
DAC Register Loaded with All 1s.
0.004
50
50
200
1
∆V
DD
=
±
5%
DB0–DB11 = 0 V;
WR, CS
= 0 V
DYNAMIC PERFORMANCE
Current Settling Time
2
To 1/2 LSB. OUT1 Load = 100
Ω,
C
EXT
= 13 pF. DAC Output Measured
from Falling Edge of
WR, CS
= 0 V.
Propagation Delay
2
(from Digital
Input Change to 90%
of Final Analog Output)
Digital-to-Analog Glitch Impulse
AC Feedthrough
2, 4
At OUT1
REFERENCE INPUT
Input Resistance
(Pin 19 to GND)
ANALOG OUTPUTS
Output Capacitance
2
C
OUT1
C
OUT1
DIGITAL INPUTS
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input Current
5
I
IN
Input Capacitance
2
DB0–DB11,
WR, CS
SWITCHING CHARACTERISTICS
Chip Select to Write Setup Time
t
CS
Chip Select to Write Hold Time
t
CH
Write Pulse Width
t
WR
Data Setup Time
t
DS
Data Hold Time
t
DH
POWER SUPPLY
V
DD
I
DD
2
All
All
200
5
–
–
150
5
–
–
ns max
nV sec typ
OUT1 Load = 100
Ω,
C
EXT
= 13 pF
3
V
REF
= AGND. OUT1 Load = 100
Ω,
Alternately Loaded with All 0s and 1s.
V
REF
=
±
10 V, 10 kHz Sine Wave
Input Resistance TC = –300 ppm/°C typ
Typical Input Resistance = 15 kΩ
All
All
5
10
20
5
10
20
5
10
20
5
10
20
mV p-p typ
kΩ min
kΩ max
All
70
150
70
150
70
150
70
150
pF max
pF max
DB0–DB11 = 0 V,
WR, CS
= 0 V
DB0–DB11 = V
DD
,
WR, CS
= 0 V
All
All
All
All
K, B, L, C
T, U
All
K, B, L, C
T, U
All
All
All
All
2.4
0.8
±
1
8
100
100
0
100
100
100
5
5
2
100
10
2.4
0.8
±
10
8
130
170
0
130
170
150
5
5
2
100
10
13.5
1.5
±
1
8
75
75
0
75
75
60
5
15
2
100
10
13.5
1.5
±
10
8
85
95
0
85
95
80
5
15
2
100
10
V min
V max
µA
max
pF max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
V
mA max
µA
max
µA
typ
±
5% For Specified Performance
All Digital Inputs V
IL
or V
IH
All Digital Inputs 0 V or V
DD
All Digital Inputs 0 V or V
DD
See Timing Diagram
V
IN
= 0 or V
DD
t
CS
≥
t
WR
, T
CH
≥
0
NOTES
1
Temperature range as follows: K, L Versions = 0°C to +70°C; B, C Versions = –25°C to +85°C; T, U Versions = –55°C to +125°C.
2
Sample tested to ensure compliance.
3
DB0–DB11 = 0 V to V
DD
or V
DD
to 0 V.
4
Feedthrough can be further reduced by connecting the metal lid on the ceramic package to DGND.
6
Logic inputs are MOS gates. Typical input current (+25°C) is less than 1 nA.
Specifications subject to change without notice.
–2–
REV. C
AD7545A
WRITE CYCLE TIMING DIAGRAM
ABSOLUTE MAXIMUM RATINGS*
(T
A
= + 25°C unless otherwise noted)
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
Digital Input Voltage to DGND . . . . . . . –0.3 V, V
DD
+0.3 V
V
RFB
, V
REF
to DGND . . . . . . . . . . . . . . . . . . . . . . . . .
±
25 V
V
PIN1
to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+0.3 V
Power Dissipation (Any Package) to 75°C . . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature Range
Commercial (KN, LN, KP, LP) Grades . . . 0°C to +70°C
Industrial (BQ, CQ, BE, CE) Grades . . . . –25°C to +85°C
Extended (TQ, UQ, TE, UE) Grades . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are removed.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Temperature
Range
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Relative
Gain
Accuracy
Error
T
MIN
–T
MAX
T
MIN
–T
MAX
±
1/2
±
1/2
±
1/2
±
1/2
±
1/2
±
1/2
±
1/2
±
1/2
±
1/2
±
1/2
±
1/2
±
1/2
±
1/2
±
4
±
2
±
4
±
4
±
2
±
4
±
2
±
4
±
2
±
4
±
2
±
4
±
2
Package
Options
2
N-20
N-20
R-20
P-20A
P-20A
Q-20
Q-20
E-20A
E-20A
Q-20
Q-20
E-20A
E-20A
Model
1
AD7545AKN
AD7545ALN
AD7545AKR
AD7545AKP
AD7545ALP
AD7545ABQ
AD7545ACQ
AD7545ABE
AD7545ACE
AD7545ATQ
AD7545AUQ
AD7545ATE
AD7545AUE
NOTES
1
To order MIL-STD-883, Class B process parts, add /883B to part number.
Contact local sales office for military data sheet.
2
E = Leadless Ceramic Chip Carrier (LCCC); N = Plastic DIP; P = Plastic
Leaded Chip Carrier (PLCC); Q = Cerdip; R = Small Outline IC.
REV. C
–3–
AD7545A
CIRCUIT INFORMATION—D/A CONVERTER SECTION
Figure 1 shows a simplified circuit of the D/A converter section
of the AD7545A, and Figure 2 gives an approximate equivalent
circuit. Note that the ladder termination resistor is connected to
AGND. R is typically 15 kΩ.
The binary weighted currents are switched between the OUT1
bus line and AGND by N-channel switches, thus maintaining a
constant current in each ladder leg independent of the switch
state.
input buffers operate in their linear region and draw current
from the power supply. To minimize power supply currents it is
recommended that the digital input voltages be as close to the
supply rails (V
DD
and DGND) as is practically possible.
The AD7545A may be operated with any supply voltage in the
range 5
≤
V
DD
≤
15 volts. With V
DD
= +15 V the input logic
levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.
BASIC APPLICATIONS
Figures 4 and 5 show simple unipolar and bipolar circuits using
the AD7545A. Resistor R1 is used to trim for full scale. The L,
C, U grades have a guaranteed maximum gain error of
±
1 LSB
at +25°C, and in many applications it should be possible to
dispense with gain trim resistors altogether. Capacitor C1 pro-
vides phase compensation and helps prevent overshoot and
ringing when using high speed op amps. Note that all the cir-
cuits of Figures 4, 5 and 6 have constant input impedance at the
V
REF
terminal.
The circuit of Figure 4 can either be used as a fixed reference
D/A converter so that it provides an analog output voltage in the
range 0 to –V
IN
(note the inversion introduced by the op amp)
or V
IN
can be an ac signal in which case the circuit behaves as
an attenuator (2-Quadrant Multiplier). V
IN
can be any voltage
in the range –20
≤
V
IN
≤
+20 volts (provided the op amp can
handle such voltages) since V
REF
is permitted to exceed V
DD
.
Table II shows the code relationship for the circuit of Figure 4.
Figure 1. Simplified D/A Circuit of AD7545A
The capacitance at the OUT1 bus line, C
OUT1
, is code-
dependent and varies from 70 pF (all switches to AGND) to
150 pF (all switches to OUT1).
One of the current switches is shown in Figure 2. The input
resistance at V
REF
(Figure 1) is always equal to R. Since R
IN
at
the V
REF
pin is constant, the reference terminal can be driven by
a reference voltage or a reference current, ac or dc, of positive or
negative polarity. (If a current source is used, a low temperature
coefficient external R
FB
is recommended to define scale factor.)
Figure 4. Unipolar Binary Operation
Table I. Recommended Trim Resistor Values vs. Grades
Trim Resistor
Figure 2. N-Channel Current Steering Switch
CIRCUIT INFORMATION—DIGITAL SECTION
K/B/T
200
Ω
68
Ω
L/C/U
100
Ω
33
Ω
R1
R2
Figure 3 shows the digital structure for one bit.
The digital signals CONTROL and
CONTROL
are generated
from
CS
and
WR.
Table II. Unipolar Binary Code Table for Circuit of Figure 4
Binary Number in
DAC Register
Analog Output
4095
–V
IN
4096
1111
1111
1111
1000
Figure 3. Digital Input Structure
0000
0000
–V
IN
2048
4096
= –1/2 V
IN
1
4096
The input buffers are simple CMOS inverters designed such
that when the AD7545A is operated with V
DD
= 5 V, the buffers
convert TTL input levels (2.4 V and 0.8 V) into CMOS logic
levels. When V
IN
is in the region of 2.0 volts to 3.5 volts, the
–4–
0000
0000
0000
0000
0001
0000
–V
IN
0 Volts
REV. C
AD7545A
Figure 5 and Table III illustrate the recommended circuit and
code relationship for bipolar operation. The D/A function itself
uses offset binary code and inverter U
1
on the MSB line con-
verts twos complement input code to offset binary code. If ap-
propriate, inversion of the MSB may be done in software using
an exclusive –OR instruction and the inverter omitted. R3, R4
and R5 must be selected to match within 0.01%, and they
should be the same type of resistor (preferably wire-wound or
metal foil), so that their temperature coefficients match. Mis-
match of R3 value to R4 causes both offset and full-scale error.
Mismatch of R5 to R4 and R3 causes full-scale error.
Figure 6. 12-Bit Plus Sign Magnitude Converter
Table IV. 12-Bit Plus Sign Magnitude Code Table for Circuit
of Figure 6
Sign
Bit
Binary Numbers in
DAC Register
Analog Output
4095
+ V
IN
×
4096
0 Volts
0 Volts
0
0
1
1
Figure 5. Bipolar Operation (Twos Complement Code)
Table III. Twos Complement Code Table for Circuit of
Figure 5
1111 1111 1111
0000 0000 0000
0000 0000 0000
1111 1111 1111
4095
– V
IN
×
4096
Note: Sign bit of “0” connects R3 to GND.
APPLICATIONS HINTS
Data Input
0111
1111
1111
Analog Output
2047
+V
IN
×
2048
1
+V
IN
×
2048
0 Volts
1
–V
IN
×
2048
2048
–V
IN
×
2048
0000
0000
1111
0000
0000
1111
0001
0000
1111
1000
0000
0000
Output Offset:
CMOS D/A converters such as Figures 4, 5
and 6 exhibit a code dependent output resistance which, in turn,
can cause a code dependent error voltage at the output of the
amplifier. The maximum amplitude of this error, which adds
to the D/A converter nonlinearity, depends on V
OS
, where V
OS
is the amplifier input offset voltage. To maintain specified accuracy
with V
REF
at 10 V, it is recommended that V
OS
be no greater than
0.25 mV, or (25
×
10
–6
) (V
REF
), over the temperature range of
operation. Suitable op amps are AD517 and AD711. The AD517
is best suited for fixed reference applications with low band-
width requirements: it has extremely low offset (150
µV
max for
lowest grade) and in most applications will not require an offset
trim. The AD711 has a much wider bandwidth and higher slew
rate and is recommended for multiplying and other applications
requiring fast settling. An offset trim on the AD711 may be
necessary in some circuits.
General Ground Management:
AC or transient voltages
between AGND and DGND can cause noise injection into the
analog output. The simplest method of ensuring that voltages at
AGND and DGND are equal is to tie AGND and DGND
together at the AD7545A. In more complex systems where the
AGND and DGND intertie is on the backplane, it is recom-
mended that two diodes be connected in inverse parallel between
the AD7545A AGND and DGND pins (1N914 or equivalent).
Figure 6 and Table IV show an alternative method of achieving
bipolar output. The circuit operates with sign plus magnitude
code and has the advantage that it gives 12-bit resolution in
each quadrant compared with 11-bit resolution per quadrant for
the circuit of Figure 5. The AD7592 is a fully protected CMOS
change-over switch with data latches. R4 and R5 should match
each other to 0.01% to maintain the accuracy of the D/A con-
verter. Mismatch between R4 and R5 introduces a gain error.
Refer to Reference 1 (supplemental application material) for
additional information on these circuits.
REV. C
–5–
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