FINAL
Am28F010A
1 Megabit (131,072 x 8-Bit) CMOS 12.0 Volt, Bulk Erase
Flash Memory with Embedded Algorithms
DISTINCTIVE CHARACTERISTICS
s
High performance
— 90 ns maximum access time
s
CMOS low power consumption
— 30 mA maximum active current
— 100
µA
maximum standby current
— No data retention power consumption
s
Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts
— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP
s
100,000 write/erase cycles minimum
s
Write and erase voltage 12.0 V
±5%
s
Latch-up protected to 100 mA from –1 V to
V
CC
+1 V
Advanced
Micro
Devices
s
Embedded Erase Electrical Bulk Chip-Erase
— Three seconds typical chip-erase including
pre-programming
s
Embedded Program
— 14
µs
typical byte-program including time-out
— Two seconds typical chip program
s
Command register architecture for
microprocessor/microcontroller compatible
write interface
s
On-chip address and data latches
s
Advanced CMOS flash memory technology
— Low cost single transistor memory cell
s
Embedded algorithms for completely
self-timed write/erase operations
GENERAL DESCRIPTION
The Am28F010A is a 1 Megabit Flash memory organ-
ized as 128K bytes of 8 bits each. AMD’s Flash
memories offer the most cost-effective and reliable
read/write non- volatile random access memory. The
Am28F010A is packaged in 32-pin PDIP, PLCC, and
TSOP versions. It is designed to be reprogrammed
and erased in-system or in standard EPROM program-
mers. The Am28F010A is erased when shipped from
the factory.
The standard Am28F010A offers access times as fast
as 90 ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the Am28F010A has separate chip enable (CE) and out-
put enable (OE) controls.
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F010A uses a command register to manage this
functionality, while maintaining a standard JEDEC
Flash standard 32-pin pinout. The command register al-
lows for 100% TTL level control inputs and fixed power
supply levels during erase and programming, while
maintaining maximum EPROM compatibility.
AMD’s Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles. The
AMD cell is designed to optimize the erase and pro-
2-164
gramming mechanisms. In addition, the combination of
advanced tunnel oxide processing and low internal
electric fields for erase and programming operations
produces reliable cycling. The Am28F010A uses a
12.0 V
±
5% V
PP
high voltage input to perform the erase
and programming functions.
The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 milliamps on
address and data pins from –1 V to V
CC
+1 V.
Embedded Program
The Am28F010A is byte programmable using the Em-
bedded Programming algorithm. The Embedded Pro-
gramming algorithm does not require the system to
time-out or verify the data programmed. The typical
room temperature programming time of the
Am28F010A is two seconds.
Embedded Erase
The entire chip is bulk erased using the Embedded
Erase algorithm. The Embedded Erase algorithm auto-
matically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internal to the device. Typical erasure at room
Publication#
16778
Rev.
C
Amendment
/0
Issue Date:
November 1995
AMD
temperature is accomplished in three seconds, includ-
ing preprogramming.
AMD’s Am28F010A is entirely pin and software compat-
ible with AMD Am28F020A Flash memory.
Embedded Programming Algorithm vs.
Flashrite Programming Algorithm
The Flashrite Programming algorithm requires the user
to write a program set-up command, a program com-
mand (program data and address), and a program verify
command followed by a read and compare operation.
The user is required to time the programming pulse
width in order to issue the program verify command. An
integrated stop timer prevents any possibility of over-
programming. Upon completion of this sequence the
data is read back from the device and compared by the
user with the data intended to be written; if there is not a
match, the sequence is repeated until there is a match or
the sequence has been repeated 25 times.
AMD’s Embedded Programming algorithm requires the
user to only write a program set-up command and a pro-
gram command (program data and address). The
device automatically times the programming pulse
width, provides the program verify and counts the
number of sequences. A status bit,
Data
Polling, pro-
vides feedback to the user as to the status of the
programming operation.
Embedded Erase Algorithm vs. Flasherase Erase
Algorithm
The Flasherase Erase algorithm requires the device to
be completely programmed prior to executing an erase
command. To invoke the erase operation the user writes
an erase set-up command, an erase command, and an
erase verify command. The user is required to time the
erase pulse width in order to issue the erase verify com-
mand. An integrated stop timer prevents any possibility
of overerasure. Upon completion of this sequence the
data is read back from the device and compared by the
user with erased data. If there is not a match, the
sequence is repeated until there is a match or the
sequence has been repeated 1,000 times.
AMD’s Embedded Erase algorithm requires the user to
only write an erase set-up command and erase com-
mand. The device will automatically pre-program and
verify the entire array. Then the device automatically
times the erase pulse width, provides the erase verify
and counts the number of sequences. A status bit,
Data
Polling, provides feedback to the user as to the status of
the erase operation.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as inputs to an internal state-machine which
controls the erase and programming circuitry. During
write cycles, the command register internally latches ad-
dress and data needed for the programming and erase
operations. For system design simplification, the
Am28F010A is designed to support either
WE
or
CE
controlled writes. During a system write cycle, ad-
dresses are latched on the falling edge of
WE
or
CE
whichever occurs last. Data is latched on the rising edge
of
WE
or
CE
whichever occurs first. To simplify the fol-
lowing discussion, the
WE
pin is used as the write cycle
control pin throughout the rest of this text. All setup and
hold times are with respect to the
WE
signal.
AMD’s Flash technology combines years of EPROM
and EEPROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The
Am28F010A electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are pro-
grammed one byte at a time using the EPROM program-
ming mechanism of hot electron injection.
Am28F010A
2-165
AMD
BLOCK DIAGRAM
DQ0–DQ7
V
CC
V
SS
V
PP
Erase
Voltage
Switch
State
Control
Command
Register
CE
OE
Embedded
Algorithms
Y-Decoder
Program/Erase
Pulse Timer
A0–A16
Y-Gating
To Array
Input/Output
Buffers
WE
Program
Voltage
Switch
Chip Enable
Output Enable
Logic
Data
Latch
Low V
CC
Detector
Address
Latch
X-Decoder
1,048,576
Bit
Cell Matrix
16778C-1
PRODUCT SELECTOR GUIDE
Family Part No.
Ordering Part No:
±10%
V
CC
Tolerance
±5%
V
CC
Tolerance
Max Access Time (ns)
CE
(E) Access (ns)
OE
(G) Access (ns)
-90
-95
90
90
35
120
120
50
150
150
55
200
200
55
250
250
55
-120
Am28F010A
-150
-200
-250
2-166
Am28F010A
AMD
CONNECTION DIAGRAMS
PDIP
V
PP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A12
A15
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
DQ3
DQ1
DQ2
DQ4
DQ5
DQ6
VSS
A16
WE
(W)
NC
A14
A13
A8
A9
A11
OE
(G)
A10
CE
(E)
DQ7
DQ6
DQ5
DQ4
DQ3
16778C-2
PLCC*
4 3 2
1 32 31 30
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
(G)
A10
CE
(E)
DQ7
VPP
VCC
WE
(W)
NC
16778C-3
Notes:
Pin 1 is marked for orientation.
Am28F010A
2-167
AMD
CONNECTION DIAGRAMS (continued)
OE
A10
CE
D7
D6
D5
D4
D3
VSS
D2
D1
D0
A0
A1
A2
A3
A11
A9
A8
A13
A14
A17
WE
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-Pin TSOP — Standard Pinout
OE
A10
CE
D7
D6
D5
D4
D3
VSS
D2
D1
D0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
A17
WE
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
16778C-4
32-Pin TSOP — Reverse Pinout
LOGIC SYMBOL
17
A0–A16
DQ0–DQ7
8
CE
(E)
OE
(G)
WE
(W)
16778C-5
2-168
Am28F010A
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