P1014CXN5HFA datasheet, PDF - EEWORLD Datasheet

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P1014CXN5HFA: Description32-BIT, 800 MHz, RISC PROCESSOR, PBGA425, 19 X 19 MM, 1.90 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, TEPBGA-425; CategoryThe embedded processor and controller Microcontrollers and processors; File Size802KB，100 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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P1014CXN5HFA Overview

32-BIT, 800 MHz, RISC PROCESSOR, PBGA425, 19 X 19 MM, 1.90 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, TEPBGA-425

P1014CXN5HFA Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	BGA
package instruction	FBGA,
Contacts	425
Reach Compliance Code	unknown
Address bus width
bit size	32
boundary scan	YES
maximum clock frequency	100 MHz
External data bus width
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B425
JESD-609 code	e2
length	19 mm
low power mode	YES
Number of terminals	425
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Package shape	SQUARE
Package form	GRID ARRAY, FINE PITCH
Maximum seat height	1.9 mm
speed	800 MHz
Maximum supply voltage	1.05 V
Minimum supply voltage	0.95 V
Nominal supply voltage	1 V
surface mount	YES
technology	CMOS
Terminal surface	TIN SILVER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	19 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC
Base Number Matches	1

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Freescale Semiconductor

Data Sheet: Advance Information

Document Number: P1014EC

Rev. 4, 05/2014

P1014

P1014 QorIQ Integrated

Processor Hardware

Specifications

The following list provides an overview of the P1014 feature

set:

• High-performance 32-bit Book E-enhanced core based on

the Power Architecture technology:

– 36-bit physical addressing

– Double-precision floating-point support

– 32-Kbyte L1 instruction cache and 32-Kbyte L1 data

cache

– 400- to 1000-MHz clock frequency

• 256-Kbyte L2 cache with ECC. Also configurable as

SRAM and stashing memory

• Two enhanced three-speed Ethernet controllers (eTSECs)

– 10/100/1000 Mbps support

– TCP/IP acceleration, quality of service, and

classification capabilities

– IEEE Std 1588™ support

– RGMII, SGMII

– eTSEC1 supports both RGMII/SGMII interfaces and

eTSEC2 support SGMII interface

• High-speed interfaces supporting the following

multiplexing options:

– Two PCI Express 1.1 interfaces

– Two SATA Revision 2.0 interfaces

– Five lanes of high-speed serial interfaces to be shared

between PCI Express, SATA, and SGMII

• High-speed USB controller (USB 2.0)

– Host and device support

– On-chip USB 2.0 high-speed PHY

– Enhanced host controller interface (EHCI)

– ULPI interface

• Enhanced secure digital host controller (SD/MMC)

• Enhanced serial peripheral interface (eSPI)

• Integrated security engine (ULE CAAM)

– Protocol support includes DES, AES, RNG, CRC,

MDE, PKE, SHA, and MD5.

• DDR3/DDR3L SDRAM memory controller supports and

16-bit with ECC

TePBGA1-425

19 mm x 19 mm

• Programmable interrupt controller (PIC) compliant with

OpenPIC standard

• One 4-channel DMA controller

• Two I

C interfaces

• Four UART interfaces

• Integrated Flash controller (IFC)

• TDM

• 16 general-purpose I/O signals

• Operating temperature (Ta - T

) range: 0–105 C (standard)

and –40 C to 105 C (extended)

• 19



19 mm 425-ball wirebond TePBGA-1 package with

0.8 mm pitch

This document contains information on a new product. Specifications and information herein

are subject to change without notice.

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