DSC2111
DSC2211
Datasheet
Low-Jitter I
2
C/SPI Programmable Dual CMOS Oscillator
General Description
The DSC2111 and DSC2211 series of
programmable, high-performance dual CMOS
oscillators utilizes a proven silicon MEMS
technology to provide excellent jitter and
stability while incorporating high output
frequency flexibility and drive strength
control. DSC2111 and DSC2211 allow the
user to independently modify the frequency
of each output and CMOS drive strength
using I
2
C or SPI interface, respectively. User
can also select from two pre-programmed
default output frequencies using the control
pin.
DSC2111 and DSC2211 are packaged in 14-
pin 3.2x2.5 mm QFN packages and available
in temperature grades from Ext. Commercial
to Automotive.
Features
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±25, ±50 ppm
Wide Temperature Range
o
Automotive: -55° to 125° C
o
Ext. Industrial: -40° to 105° C
o
Industrial: -40° to 85° C
o
Ext. commercial: -20° to 70° C
High Supply Noise Rejection: -50 dBc
Two Independent CMOS Outputs
I
2
C/SPI Programmable Freq & Drive
Short Lead Times: 2 Weeks
Wide Frequency Range:
o
CMOS Output: 2.3 to 170 MHz
Miniature Footprint of 3.2x2.5mm
Excellent Shock & Vibration Immunity
o
Qualified to MIL-STD-883
High Reliability
o
20x better MTF than quartz oscillators
Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
Block Diagram
Applications
Storage Area Networks
o
SATA, SAS, Fibre Channel
Passive Optical Networks
o
EPON, 10G-EPON, GPON, 10G-PON
Ethernet
o
1G, 10GBASE-T/KR/LR/SR, and FCoE
HD/SD/SDI Video & Surveillance
PCI Express
Pin #
3
5
6
7
DSC2111 (I
2
C)
NC
SDA
SCL
CS_bar
DSC2211 (SPI)
SCLK
MOSI
MISO
SS
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DSC2111 DSC2211
Page 1
MK-Q-B-P-D-12050102
DSC2111
DSC2211
Low-Jitter I
2
C/SPI Programmable Dual CMOS Oscillator
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
Enable
NC
NC
SCLK
GND
SDA
MOSI
SCL
MISO
CS_bar
SS
Output1
NC
NC
Output2
VDD2
VDD
FS
Pin
Type
I
NA
NA
I
Power
I
I
O
I
I
O
NA
NA
O
Power
Power
I
Description
Enables outputs when high and disables when low
Leave unconnected or grounded
DSC2111: Leave unconnected or grounded
DSC2211: Serial clock from master
Ground
DSC2111: I
2
C Serial Data
DSC2211: SPI Serial Data from Master to Slave
DSC2111: I
2
C Serial Clock
DSC2211: SPI Serial Data from Slave to Master
DSC2111: I
2
C Chip Select (Active Low)
DSC2211: SPI Slave Select (Active Low)
CMOS output 1
Leave unconnected or grounded
Leave unconnected or grounded
CMOS output 2
Power Supply for CMOS Output 2
Power Supply
Default output clock frequency bit
Operational Description
The DSC2111/2211 is a dual CMOS oscillator
consisting of a MEMS resonator and a support
PLL IC. The outputs are generated through
independent 8-bit programmable dividers from
the output of the internal PLL.
DSC2111/2211 allows for easy programming
of the output frequencies using I
2
C/SPI
interface. Upon power-up, the initial output
frequencies are controlled by an internal pre-
programmed memory (OTP). This memory
stores all coefficients required by the PLL for
two different default frequency pairs. The
control pin (FS) selects the initial pair. Once
the device is powered up, a new output
frequency pair can be programmed using
I
2
C/SPI pins.
Programming details are
provided in the
Programming Guide.
Standard
default
frequency
pairs
are
described in the following sections. Discera
supports customer defined versions.
The DSC2111/2211 has independent control
of the output voltage levels of the two
outputs. The high voltage level of Output 1 is
equal to the main supply voltage, VDD (pin
13). VDD2 (pin 12) sets the high voltage
level of Output 2. VDD2 must be equal to or
less than VDD. VDD2 can be as low as 1.65V.
When Enable (pin 1) is floated or connected to
VDD, the DSC2111/2211 is in operational
mode. Driving Enable to ground will disable
both output drivers (hi-impedance mode).
The DSC2111/2211 has programmable output
drive strength, which can be controlled via
I
2
C/SPI. Table 1 displays typical rise / fall
times for the output with a 15pf load
capacitance as a function of these control bits
at VDD=3.3V and room temperature.
Table 1. Rise/Fall times for drive strengths
Output Drive Strength Bits
[OXS2, OXS1, OXS0] - Default [111]
X=1 for output1, and 2 for output2
000
001
010
011
100
101
110
111
tr
tf
(ns)
(ns)
2.1
2.5
1.7
2.4
1.6
2.4
1.4
2
1.3
1.8
1.3
1.6
1.2
1.3
1.1
1.3
Output Clock Frequencies
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DSC2111 DSC2211
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MK-Q-B-P-D-12050102
DSC2111
DSC2211
Low-Jitter I
2
C/SPI Programmable Dual CMOS Oscillator
Table 2 lists the standard default frequency configurations and the associated ordering information
to be used in conjunction with the ordering code. Customer defined combinations are available.
Table 2. Pre-programmed pin-selectable output frequency pairs
Ordering
Info
E0001
E0002
E0004
E0005
E0006
E0007
E0008
EXXXX
Freq
(MHz)
f
OUT1
f
OUT2
f
OUT1
f
OUT2
f
OUT1
f
OUT2
f
OUT1
f
OUT2
f
OUT1
f
OUT2
f
OUT1
f
OUT2
f
OUT1
f
OUT2
f
OUT1
f
OUT2
Select Bit [FS] –
Default is [1]
0
1
27
25
24
106.25
25
24
24
25
25
27
13.5
24
40
40
200
125
100
100
75
75
0*
0*
74.175
37.0875
0*
0*
40
128
Contact factory for additional
configurations.
Frequency select bit are weakly tied high so if left unconnected the default setting will be [1] and
the device will output the associated frequency highlighted in
Bold.
0* – denotes invalid selection, output frequency is not specified.
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DSC2111 DSC2211
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MK-Q-B-P-D-12050102
DSC2111
DSC2211
Low-Jitter I
2
C/SPI Programmable Dual CMOS Oscillator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Ordering Code
Condition
Prog Mode
1: I
2
C bus
2: SPI bus
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
Temp Range
E: -20 to 70
I: -40 to 85
L: -40 to 105
M: -55 to 125
Packing
T: Tape & Reel
: Tube
DSC2
1
11
F I 2
40sec max.
Package
F: 3.2x2.5mm
-
xxxxx
T
Freq (MHz)
See Freq. table
Stability
1: ±50ppm
2: ±25ppm
Note: 1000+ years of data retention on internal memory
Specifications
(Unless specified otherwise: T=25° C)
Parameter
Supply Voltage
1
Supply Voltage (Output2)
1
Supply Current
Supply Current
2
Frequency Stability
Aging
Startup Time
3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor
2
Output Logic Levels
Output logic high
Output logic low
Output Transition time
4
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
5
Integrated Phase Noise
Notes:
1.
2.
3.
4.
5.
Condition
V
DD
V
DD2
I
DD
I
DD
Δf
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
Pull-up exists on all digital IO
EN pin low – outputs are disabled
EN pin high – outputs are enabled
C
L
=15Ω, F
O1
=F
O2
=125 MHz
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
1 year @25°C
T=25°C
Min.
2.25
1.65
Typ.
Max.
3.6
3.6
Unit
V
V
mA
mA
21
32
23
±25
±50
±5
5
0.75xV
DD
-
-
0.25xV
DD
5
20
40
ppm
ppm
ms
V
ns
ns
kΩ
CMOS Outputs
V
OH
V
OL
t
R
t
F
f
0
SYM
J
PER
J
CC
I=±6mA
20% to 80%
C
L
=15pf
Commercial/Industrial temp range
Automotive temp range
F
O1
=F
O2
=125 MHz
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
2.3
45
3
0.3
0.38
1.7
0.9xV
DD
-
1.1
1.4
-
0.1xV
DD
2
2
170
100
55
V
ns
MHz
%
ps
RMS
ps
RMS
2
Pin 4 V
DD
should be filtered with 0.01uf capacitor.
Output is enabled if Enable pad is floated or not connected.
t
su
is time to 100PPM stable output frequency after V
DD
is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
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DSC2111 DSC2211
Page 4
MK-Q-B-P-D-12050102
DSC2111
DSC2211
Low-Jitter I
2
C/SPI Programmable Dual CMOS Oscillator
Nominal Performance Parameters
(Unless specified otherwise: T=25° C, V
DD
=3.3 V)
2.5
25MHz-CMOS
Phase Jitter (ps RMS)
2.0
50MHz-CMOS
106MHz-CMOS
125MHz-CMOS
1.5
1.0
0.5
0.0
0
200
400
600
800
1000
Low-end of integration BW: x kHz to 20 MHz
CMOS Phase jitter (integrated phase noise)
Output Waveform: CMOS
t
R
V
OH
t
F
Output
V
OL
1/f
o
t
DA
V
IH
t
EN
Enable
V
IL
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DSC2111 DSC2211
Page 5
MK-Q-B-P-D-12050102
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