Product Specification
PE4307
Product Description
The PE4307 is a high linearity, 5-bit RF Digital Step
Attenuator (DSA) covering a 15.5 dB attenuation range in
0.5 dB steps. The device is pin compatible with the PE430x
series. This 75-ohm RF DSA provides both parallel (latched
or direct mode) and serial CMOS control interface, operates
on a single 3-volt supply and maintains high attenuation
accuracy over frequency and temperature. It also has a
unique control interface that allows the user to select an
initial attenuation state at power-up. The PE4307 exhibits
very low insertion loss and low power consumption. This
functionality is delivered in a 4x4 mm QFN footprint.
75Ω RF Digital Attenuator
5-bit, 15.5 dB, 1 – 2000 MHz
Features
Attenuation: 0.5 dB steps to 15.5 dB
Flexible parallel and serial programming
interfaces
Latched or direct mode
Unique power-up state selection
Positive CMOS control logic
High attenuation accuracy and linearity
over temperature and frequency
Very low power consumption
Single-supply operation
75Ω impedance
Pin compatible with PE430x series
Packaged in a 20-lead 4x4 mm QFN
Figure 1. Functional Schematic Diagram
RF Input
Parallel Control
Serial Control
Power-Up Control
5
BS
C
3
Control Logic Interface
1
Table 1. Electrical Specifications @ +25°C, V
DD
= 3.0V
O
Parameter
Test Condition
E
W
O
IT
RF Output
71-0007
Switched Attenuator Array
Frequency
H
Minimum
1
-
-
30
-
10
-
1.4
-
34
52
13
-
Typical
Maximum
2000
1.95
±(0.15 + 4% of atten setting)
Not to exceed +0.25 dB
-
-
-
1
PE
43
1
Figure 2. Package Type
20-lead 4x4 mm QFN
LE
1 MHz ≤ 1.2 GHz
1 MHz ≤ 1.2 GHz
1 MHz ≤ 1.2 GHz
1 MHz ≤ 1.2 GHz
1 MHz ≤ 1.2 GHz
The PE4307 is manufactured on Peregrine’s UltraCMOS
®
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
4
TE
Unit
MHz
dB
dB
dB
dBm
dBm
dB
s
Operation Frequency
Insertion Loss
1
1 dB Compression
3,4
Input IP3
1,2,4
Return Loss
Switching Speed
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Notes: 1. Device Linearity will begin to degrade below 1 MHz
2. Max input rating in
Table 3
& Figures on Pages 4 to 6 for data across frequency
3. Note Absolute Maximum in
Table 3
4. Measured in a 50Ω system
EP
LA
Zo = 75 ohms
Attenuation Accuracy
Any Bit or Bit
Combination
Two-tone inputs up to
+18 dBm
50% control to 0.5 dB
of final value
©2003-2013 Peregrine Semiconductor Corp. All rights reserved.
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PE4307
Product Specification
Figure 15. Pin Configuration (Top View)
GND
C0.5
C1
C2
C4
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
Parameter/Condition
Power supply voltage
Voltage on any input
Storage temperature range
Input power (50Ω)
ESD voltage (Human Body
Model)
Min
-0.3
-0.3
-65
Max
4.0
V
DD
+
0.3
150
+30
500
Unit
V
V
°C
dBm
V
20
19
18
17
N/C
RF1
Data
Clock
LE
16
1
2
3
4
5
15
C8
RF2
P/S
Vss/GND
GND
T
ST
P
IN
V
ESD
20-lead
QFN
4x4mm
Exposed Solder Pad
14
13
12
11
Table 4. Operating Ranges
Parameter
Min
2.7
V
DD
Power Supply
Voltage
I
DD
Power Supply
Current
Digital Input High
Digital Input Low
TE
Typ
3.0
Max
3.3
Unit
V
μA
V
V
μA
dBm
°C
PUP2
GND
V
DD
N/C
V
DD
10
6
7
8
9
Table 2. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
N/C
RF1
Data
Clock
LE
V
DD
N/C
PUP2
V
DD
GND
GND
No connect
RF port (Note 1)
Serial interface clock input
Latch Enable input (Note 2)
Power supply pin
No connect
Description
Digital Input Leakage
Serial interface data input (Note 4)
Input Power
Temperature range
Power-up selection bit
Power supply pin
Ground connection
Ground connection
BS
C
V
ss
/GND
P/S
C8
C4
C2
C1
Negative supply voltage or GND
connection (Note 3)
Parallel/Serial mode select
RF port (Note 1)
RF2
Attenuation control bit, 8 dB
Attenuation control bit, 4 dB
Attenuation control bit, 2 dB
Ground connection.
Attenuation control bit, 1 dB
E
W
O
GND
C0.5
Attenuation control bit, 0.5 dB
Ground for proper operation
Paddle
EP
LA
GND
Notes: 1. Both RF ports must be held at 0 V
DC
or DC blocked with an external
series capacitor
2. Latch Enable (LE) has an internal 100 kΩ resistor to V
DD
3. Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to V
SS
(-V
DD
) to bypass and disable
internal negative voltage generator
4. Place a 10 kΩ resistor in series, as close to pin as possible to avoid
frequency resonance. See “Resistor on 3” paragraph
R
O
IT
Exposed Solder Pad Connection
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The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS
®
device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in
Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
®
devices are immune to latch-up.
Switching Frequency
The PE4307 has a maximum 25 kHz switching rate.
Resistor on Pin 3
A 10 kΩ resistor on the input to Pin 3 (see
Figure 5)
will eliminate package resonance between the RF
input pin and the digital input. Specified attenuation
error versus frequency performance is dependent
upon this condition.
Document No. 70-0161-05
│
UltraCMOS
®
RFIC Solutions
PE
43
1
1
-40
LE
0.7xV
DD
4
0.3xV
DD
+24
85
100
PE4307
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit was designed to
ease customer evaluation of the PE4307 DSA.
J9 is used in conjunction with the supplied DC cable to
supply V
DD
, GND, and –V
DD
. If use of the internal
negative voltage generator is desired, then connect –
V
DD
(black banana plug) to ground. If an external –V
DD
is desired, then apply -3V.
J1 should be connected to the LPT1 port of a PC with
the supplied control cable. The evaluation software is
written to operate the DSA in serial mode, so switch 7
(P/S) on the DIP switch SW1 should be ON with all
other switches off. Using the software, enable or
disable each attenuation setting to the desired
combined attenuation. The software automatically
programs the DSA each time an attenuation state is
enabled or disabled.
Note: Jumper J6 supplies power to the evaluation
board support circuits.
To evaluate the Power Up options, first disconnect the
control cable from the evaluation board. The control
cable must be removed to prevent the PC port from
biasing the control pins.
During power up with P/S=1 high and LE=1, the default
power-up signal attenuation is set to the value present
on the five control bits on the five parallel data inputs
(C0.5 to C8). This allows any one of the 32 attenuation
settings to be specified as the power-up state.
Figure 4. Evaluation Board Layout
Peregrine Specification 101/0112
W
During power up with P/S=0 high and LE=0, the control
bits are automatically set to one of two possible values
presented through the PUP interface. These two values
are selected by the power-up control bit, PUP2, as
shown in
Table 6.
BS
C
E
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EP
LA
O
Pins 1 and 7 are open and may be connected to any
bias.
O
IT
Note: Resistor on pin 3 is required and
should be placed as close to the part as
possible to avoid package resonance and
meet error specifications over frequency.
H
Figure 5. Evaluation Board Schematic
Peregrine Specification 102/0142
©2003-2013 Peregrine Semiconductor Corp. All rights reserved.
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PE
43
1
LE
4
TE
PE4307
Product Specification
Typical Performance Data @ 25°C, V
DD
= 3.0V
Figure 6. Insertion Loss (Zo = 75 ohms)
0
-0.5
-40C
-1
25C
Attenuation (dB)
Figure 7. Attenuation at Major steps
16
14
12
85C
15.5dB
Insertion Loss (dB)
TE
8
6
4
2
0
1dB
0.5dB
-1.5
-2
-2.5
-3
-3.5
-4
0
500
1000
RF Frequency (MHz)
10
8dB
4dB
2dB
PE
43
1
0
500
1000
RF Frequency (MHz)
0
-10
-20
-30
-40
-50
0
500
1000
RF Frequency (MHz)
LE
2000
Output Return loss (dB)
4
1500
1500
1500
2000
Figure 8. Input Return Loss at Major
Attenuation Steps (Zo = 75 ohms)
0
-5
-10
-15
O
-20
-25
-30
EP
LA
15.5dB
BS
C
4dB
8dB
Input Return Loss (dB)
E
W
O
IT
1500
2000
Figure 9. Output Return Loss at Major
Attenuation Steps (Zo = 75 ohms)
H
0
500
1000
2000
RF Frequency (MHz)
R
©2003-2013 Peregrine Semiconductor Corp. All rights reserved.
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Document No. 70-0161-05
│
UltraCMOS
®
RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4307
Product Specification
Typical Performance Data @ 25°C, V
DD
= 3.0V
Figure 10. Attenuation Error Vs. Frequency
Figure 11. Attenuation Error Vs. Attenuatio
Setting
1
10Mhz
250Mhz
500Mhz
750Mhz
1010Mhz
1210Mhz
0.5
0
0.5
Attenuation Error (dB)
-0.5
8dB
-1
15.5dB
-2
0
500
1000
RF Frequency (MHz)
PE
43
1
-1
0
2
4
6
8
10
Attenuation Setting (dB)
40
35
30
25
20
15
10
5
0
0
500
1000
RF Frequency (MHz)
LE
2000
1dB Compression (dBm)
4
12
14
16
1500
2000
-1.5
1500
Figure 12. Input IP3 vs. Frequency (Zo = 50 ohms)
55
50
Input IP3 (dBm)
45
40
35
30
25
20
EP
LA
O
0
500
BS
C
1000
60
E
1500
RF Frequency (MHz)
Note: Positive attenuation error indicates higher attenuation than target value
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W
2000
O
IT
Figure 13. Input 1 dB Compression (Zo = 50 ohms)
H
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TE
0
-0.5
Attenuation Error (dB)
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