UV PLD, 55ns, CMOS, CPGA100, WINDOWED, CERAMIC, PGA-100
| Parameter Name | Attribute value |
| Maker | Altera (Intel) |
| Parts packaging code | PGA |
| package instruction | WPGA, |
| Contacts | 100 |
| Reach Compliance Code | unknown |
| ECCN code | 3A001.A.2.C |
| Other features | LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK |
| maximum clock frequency | 33.3 MHz |
| JESD-30 code | S-CPGA-P100 |
| JESD-609 code | e4 |
| length | 33.528 mm |
| Dedicated input times | 19 |
| Number of I/O lines | 64 |
| Number of terminals | 100 |
| Maximum operating temperature | 125 °C |
| Minimum operating temperature | -55 °C |
| organize | 19 DEDICATED INPUTS, 64 I/O |
| Output function | MACROCELL |
| Package body material | CERAMIC, METAL-SEALED COFIRED |
| encapsulated code | WPGA |
| Package shape | SQUARE |
| Package form | GRID ARRAY, WINDOW |
| Programmable logic type | UV PLD |
| propagation delay | 55 ns |
| Certification status | Not Qualified |
| Filter level | MIL-STD-883 |
| Maximum seat height | 3.81 mm |
| Maximum supply voltage | 5.5 V |
| Minimum supply voltage | 4.5 V |
| Nominal supply voltage | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | MILITARY |
| Terminal surface | GOLD |
| Terminal form | PIN/PEG |
| Terminal pitch | 2.54 mm |
| Terminal location | PERPENDICULAR |
| width | 33.528 mm |
| Base Number Matches | 1 |
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