Product Brief
FW420 07
1394b PCI Link Open Host Controller Interface
F e at u r e s
n
Available in a 120-pin TQFP or
129-pin VTFSBGA lead-free
package.
1394a link and 1394b link:
— Compatible with current Microsoft
Windows® drivers and other
common applications.
— Compatible with existing and
older, 1394 consumer electronics
and peripherals products.
— Supports low-power system
designs (CMOS implementation,
power management features).
— Provides LPS, LKON, and CNA
outputs to support legacy power
management implementations.
— Cycle master and isochronous
resource manager capable.
— Supports 1394a and 1394b
acceleration features.
— Provides an 8-bit interface running
at 50 MHz for 1394a and 100 MHz
for 1394b.
n
1394 OHCI specification revision 1.0 and 1.1:
— Isochronous receive dual-buffer mode.
— Enhanced isochronous transmit skip/over
flow support.
— ack_data_error improvements for
asynchronous and physical requests.
— Enhanced CSR control register
implementation.
— Autonomous configuration ROM updates.
— Enhanced power management support,
including ack_tardy event.
— Enhanced SelfID protocol, including
selfIDComplete2 event.
— Compatible with Microsoft Windows and
MacOS® operating systems.
— 4 Kbyte isochronous transmit FIFO.
— 2 Kbyte asynchronous transmit FIFO.
— 4 Kbyte isochronous receive FIFO.
— 2 Kbyte asynchronous receive FIFO.
— Dedicated asynchronous and isochronous
descriptor-based DMA engines.
n
The FW420 07 is the LSI imple-
mentation of a high performance,
PCI bus-based open host controller
for implementation of IEEE® 1394b
compliant systems and devices.
Link layer functions are handled by
the FW420 07, utilizing the on-
chip 1394b compliant link core.
A high-performance and cost-
effective solution for connecting
and servicing multiple IEEE 1394
(1394—1995, 1394a, and 1394b)
peripheral devices can be realized.
n
PCI:
— Revision 2.3 compliant.
— 33 MHz/32-bit operation.
— Programmable burst size for PCI
data transfer.
— Supports PCI Bus Power
Management Interface
Specification v.1.1.
— Supports clockrun protocol per
PCI Mobile Design Guide.
— Global byte swap function.
Ot h e r F e at u r e s
n
I2C serial ROM interface.
CMOS process.
3.3 V operation, 5 V tolerant inputs.
n
n
FW420 Functional Block Diagram
OHCI
ASYNC
PCI BUS
PCI
CORE
LINK
CORE
PHY LINK
INTERFACE
OHCI
ISOCH
ROM I/F
O r D e r I N G I N F O r M at I O N
Device Code
L-FW420-07-T120-DB†‡
L-FW420-07-T120-DT*†‡
L-FW420-07-NV129-DB†‡
L-FW420-07-NV129-DT*†‡
* Tape-and-reel part numbers.
Package
120-Pin TQFP
120-Pin TQFP
129-Ball VTFSBGAC
129-Ball VTFSBGAC
Comcode
711009646
711009575
711009648
711009626
† Lead-free: No intentional addition of lead, and less than 1000 ppm.
‡ LSI lead-free devices are fully compliant with the Restriction of Hazardous Substances (RoHS) directive that restricts the
content of six hazardous substances in electronic equipment in the European Union. Beginning July 1, 2006, electronic
equipment sold in the European Union must be manufactured in accordance with the standards set by the RoHS
directive.
For more information and sales office locations, please visit the LSI web sites at:
lsi.com lsi.com/contacts
LSI Corporation and, LSI logo design The Communications Company, are trademarks or registered trademarks of LSI Corporation.
All other brand and product names may be trademarks of their respective companies. LSI Corporation reserves the right to make changes to any
products and services herein at any time without notice. LSI does not assume any responsibility or liability arising out of the application or use
of any product or service described herein, except as expressly agreed to in writing by LSI; nor does the purchase, lease, or use of a product or
service from LSI convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI or
of third parties.
Copyright ©2006 by LSI Corporation. All rights reserved.
September 2006
PB06-035CMPR-1 (Replaces PB06-035CMPR)
Talking
京公网安备 11010802033920号
EEWORLD
