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ICS93712YFLF-T

Description
Low Skew Clock Driver, 6 True Output(s), 6 Inverted Output(s), PDSO28, 0.209 INCH, MO-150, SSOP-28
Categorylogic    logic   
File Size388KB,6 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric View All

ICS93712YFLF-T Overview

Low Skew Clock Driver, 6 True Output(s), 6 Inverted Output(s), PDSO28, 0.209 INCH, MO-150, SSOP-28

ICS93712YFLF-T Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeSSOP
package instruction0.209 INCH, MO-150, SSOP-28
Contacts28
Reach Compliance Codecompliant
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G28
JESD-609 codee3
length10.2 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Number of functions1
Number of inverted outputs6
Number of terminals28
Actual output times6
Maximum operating temperature85 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.1 ns
Maximum seat height2 mm
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
Temperature levelOTHER
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width5.3 mm
Base Number Matches1
Integrated
Circuit
Systems, Inc.
ICS93712
Advance Information
2 DIMM DDR Fanout Buffer
Recommended Application:
DDR fan out buffer for VIA PRO 266 DDR chipset
Product Description/Features:
• Low skew, fanout buffer
• 1 to 6 differential clock distribution
• I
2
C for functional and output control
• Feedback pin for input to output synchronization
• Supports up to 2 DDR DIMMs
• Frequency support for up to 400MHz DDR, SDRAMs
• CMOS level control signal input
Switching Characteristics:
• OUTPUT - OUTPUT skew: <100ps
• Output Rise and Fall Time for DDR outputs: 650ps - 950ps
• DUTY CYCLE: 47% - 53%
• Pulse Skew: <100ps
Pin Configuration
FBOUT
GND
DDRT0
DDRC0
VDD2.5
GND
DDRT1
DDRC1
VDD2.5
BUF_IN
GND
DDRT2
DDRC2
VDD2.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
DDRT5
DDRC5
VDD2.5
GND
DDRT4
DDRC4
VDD2.5
GND
DDRT3
DDRC3
VDD2.5
SCLK
SDATA
28-Pin SSOP
Block Diagram
FB_OUT
BUF_IN
DDRT0
DDRC0
DDRT1
DDRC1
SCLK
SDATA
Control
Logic
DDRT1
DDRC2
DDRT3
DDRC3
DDRT4
DDRC4
DDRT5
DDRC5
93712 Rev - 9/08/00
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
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