PRoC™ BLE: CYBL1XX7X
Family Datasheet
Programmable Radio-on-Chip With
Bluetooth Low Energy
PRoC™ BLE is a 32-bit, 48-MHz ARM
®
Cortex
®
-M0 BLE solution with CapSense
®
, 12-bit ADC, four timer, counter, pulse-width
modulators (TCPWM), Direct memory access (DMA), thirty-six GPIOs, two serial communication blocks (SCBs), LCD, and I
2
S.
PRoC BLE includes a royalty-free BLE stack compatible with Bluetooth
®
4.2 and provides a complete, programmable, and flexible
solution for HID, remote controls, toys, beacons, and wireless chargers. In addition to these applications, PRoC BLE provides a
simple, low-cost way to add BLE connectivity to any system.
General Description
Features
Bluetooth
®
Smart Connectivity
Bluetooth 4.2 single-mode device
■
2.4-GHz BLE radio and baseband with integrated balun
■
TX output power: –18 dBm to +3 dBm
■
Received signal strength indicator (RSSI) with 1-dB resolution
■
RX sensitivity: –92 dBm
■
TX current: 15.6 mA at 0 dBm
■
RX current: 16.4 mA
■
■
■
■
■
Two serial communication blocks (SCBs) supporting I
2
C
(Master/Slave), SPI (Master/Slave), or UART
Four dedicated 16-bit TCPWMs
❐
Additional four 8-bit or two 16-bit PWMs
Programmable LVD from 1.8 V to 4.5 V
I
2
S Master interface
Wide supply-voltage range: 1.9 V to 5.5 V
3-MHz to 48-MHz internal main oscillator (IMO) with 2%
accuracy
24-MHz external clock oscillator (ECO) without load
capacitance
32-kHz WCO
36 GPIOs configurable as open drain high/low,
pull-up/pull-down, HI-Z, or strong output
Any GPIO pin can be CapSense, LCD, or analog, with flexible
pin routing
2-pin SWD
In-system flash programming support
Operating temperature range: –40 °C to +105 °C
Available in 56-pin QFN (7 mm × 7 mm) and 76-ball WLCSP
(3.52 mm × 3.91 mm) packages
Easy-to-use IDE to configure, develop, program, and test a
BLE application
Option to export the design to Keil, IAR, or Eclipse
Bluetooth Low Energy protocol stack supporting generic
access profile (GAP) Central, Peripheral, Observer, or
Broadcaster roles
❐
Switches between Central and Peripheral roles on-the-go
Standard Bluetooth Low Energy profiles and services for
interoperability
❐
Custom profile and service for specific use cases
Clock, Reset, and Supply
■
■
■
■
ARM Cortex-M0 CPU Core
32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit
multiply, operating at up to 48 MHz
■
256-KB flash memory
■
32-KB SRAM memory
■
Emulated EEPROM using flash memory
■
Watchdog timer with dedicated internal low-speed oscillator
(ILO)
■
Eight-channel direct memory access (DMA) controller
■
Programmable GPIOs
■
■
Ultra-Low-Power
1.5-µA Deep-Sleep mode with watch crystal oscillator (WCO)
on
■
150-nA Hibernate mode current with SRAM retention
■
60-nA Stop mode current with GPIO wakeup
■
Programming and Debug
■
■
Temperature and Packaging
■
■
CapSense
®
Touch Sensing with Two-Finger Gestures
Up to 36 capacitive sensors for buttons, sliders, and touchpads
■
One-finger gestures: finger tracking, scroll, inertial scroll,
edge-swipe, click, double-click
■
Two-finger gestures: scroll, inertial scroll, zoom-in, zoom-out
■
Cypress Capacitive Sigma-Delta (CSD) provides best-in-class
SNR (> 5:1) and liquid tolerance
■
Automatic hardware-tuning algorithm (SmartSense™)
■
PSoC
®
Creator™ Design Environment
■
■
Bluetooth Low Energy Protocol Stack
■
Peripherals
12-bit, 1-Msps SAR ADC with internal reference,
sample-and-hold (S/H), and channel sequencer
■
Ultra-low-power LCD segment drive for 128 segments with
operation in Deep-Sleep mode
■
■
Cypress Semiconductor Corporation
Document Number: 001-95464 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 16, 2016
PRoC™ BLE: CYBL1XX7X
Family Datasheet
More Information
Cypress provides a wealth of data at
http://www.cypress.com
to
help you to select the right PSoC device for your design, and to
help you to quickly and effectively integrate the device into your
design. For a comprehensive list of resources, see the intro-
duction page for
Bluetooth® Low Energy (BLE) Products.
Following is an abbreviated list for PRoC BLE:
■
Overview: PSoC Portfolio, PSoC Roadmap
■
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PRoC BLE,
PSoC 4 BLE, PSoC 5LP In addition, PSoC Creator includes a
device selection tool.
■
Application Notes: Cypress offers a large number of PSoC
application notes converting a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PRoC BLE are:
❐
AN94020:
Getting Started with PRoC BLE
❐
AN97060:
PSoC 4 BLE and PRoC BLE - Over-The-Air (OTA)
Device Firmware Upgrade (DFU) Guide
❐
AN91184:
PSoC 4 BLE - Designing BLE Applications
❐
AN91162:
Creating a BLE Custom Profile
❐
AN91445:
Antenna Design and RF Layout Guidelines
❐
AN96841:
Getting Started With EZ-BLE Module
❐
AN85951:
PSoC 4 CapSense Design Guide
AN95089:
PSoC 4/PRoC BLE Crystal Oscillator Selection
and Tuning Techniques
❐
AN92584:
Designing for Low Power and Estimating Battery
Life for BLE Applications
■
Technical Reference Manual (TRM) is in two documents:
❐
Architecture TRM
details each PRoC BLE functional block
❐
Registers TRM
describes each of the PRoC BLE registers
■
Development Kits:
❐
CY8CKIT-042-BLE
Pioneer Kit, is a flexible, Arduino-com-
patible, Bluetooth LE development kit for PSoC 4 BLE and
PRoC BLE.
❐
CY5676,
PRoC BLE 256KB Module, features a PRoC BLE
256KB device, two crystals for the antenna matching net-
work, a PCB antenna and other passives, while providing
access to all GPIOs of the device.
❐
CY8CKIT-142,
PSoC 4 BLE Module, features a PSoC 4 BLE
device, two crystals for the antenna matching network, a PCB
antenna and other passives, while providing access to all
GPIOs of the device.
❐
CY8CKIT-143,
PSoC 4 BLE 256KB Module, features a PSoC
4 BLE 256KB device, two crystals for the antenna matching
network, a PCB antenna and other passives, while providing
access to all GPIOs of the device.
❐
The
MiniProg3
device provides an interface for flash pro-
gramming and debug.
❐
PSoC Creator
PSoC Creator
is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the
list of component datasheets.
With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
3. Configure components using the configuration tools
system design in the main design workspace
4. Explore the library of 100+ components
2. Codesign your application firmware with the PSoC hardware,
5. Review component datasheets
using the PSoC Creator IDE C compiler
Figure 1. Multiple-Sensor Example Project in PSoC Creator Contents
1
2
3
Document Number: 001-95464 Rev. *J
4
5
Page 2 of 44
PRoC™ BLE: CYBL1XX7X
Family Datasheet
Contents
Blocks and Functionality ................................................. 4
CPU Subsystem .......................................................... 5
BLE Subsystem........................................................... 5
System Resources Subsystem ................................... 6
Peripheral Blocks ........................................................ 7
Pinouts .............................................................................. 9
Power............................................................................... 14
Low-Power Modes..................................................... 14
Development Support .................................................... 16
Documentation .......................................................... 16
Online ........................................................................ 16
Tools.......................................................................... 16
Kits ............................................................................ 16
Electrical Specifications ................................................ 17
Absolute Maximum Ratings....................................... 17
BLE Subsystem......................................................... 17
Device-Level Specifications ...................................... 20
Analog Peripherals .................................................... 25
Digital Peripherals ..................................................... 26
Memory .....................................................................
System Resources ....................................................
Ordering Information......................................................
Ordering Code Definitions .........................................
Packaging........................................................................
WLCSP Compatibility ................................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Revision History .............................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
29
30
33
33
34
36
38
40
40
41
42
42
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Document Number: 001-95464 Rev. *J
Page 3 of 44
PRoC™ BLE: CYBL1XX7X
Family Datasheet
Blocks and Functionality
The CYBL1XX7X block diagram is shown in
Figure 2.
There are five major subsystems: CPU subsystem, BLE subsystem, system
resources, peripheral blocks, and I/O subsystem.
Figure 2. Block Diagram
CPU Subsystem
P0.6
P0.7
ARM
Cortex-M0
SWD
NVIC
FLASH
256 KB
SRAM
32 KB
ROM
8 KB
CONFIG
512 B
DMA
Controller
System Interconnect
System Resources
Power
BOD
LVD
XRES
WDT
Clock Control
IMO
ILO
BLE Subsystem
Link Layer
Engine
RF PHY
WCO
ECO
XRES
XTAL32I/P6.1
XTAL32O/P6.0
XTAL24I
XTAL24O
ANT
Peripherals
GPIOs
12-Bit
SAR ADC
SCB0
I2C/UART/SPI
GPIOs
GPIOs
Peripheral Interconnect
4x TCPWM
SCB1
I2C/UART/SPI
GPIOs
GPIOs
4x PWM
LCD
GPIOs
GPIOs
I2S
CAPSENSE
I/O Subsystem
GPIOs
The PRoC BLE family includes extensive support for
programming, testing, debugging, and tracing both hardware
and firmware. The complete debug-on-chip functionality enables
full-device debugging in the final system using the standard
production device. It does not require special interfaces,
debugging pods, simulators, or emulators. Only the standard
programming connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for PRoC BLE devices. The SWD interface
is fully compatible with industry-standard third-party tools.
PRoC BLE also supports disabling the SWD interface and has a
robust flash-protection feature.
Document Number: 001-95464 Rev. *J
Page 4 of 44
PRoC™ BLE: CYBL1XX7X
Family Datasheet
CPU Subsystem
CPU
The CYBL1XX7X device is based on an energy-efficient
ARM Cortex-M0 32-bit processor, offering low power
consumption, high performance, and reduced code size using
16-bit thumb instructions. The Cortex-M0’s ability to perform
single-cycle 32-bit arithmetic and logic operations, including
single-cycle 32-bit multiplication, helps in better performance.
The inclusion of the tightly-integrated Nested Vectored Interrupt
Controller (NVIC) with 32 interrupt lines enables the Cortex-M0
to achieve a low latency and a deterministic interrupt response.
The CPU also includes a 2-pin interface, the serial wire debug
(SWD), which is a 2-wire form of JTAG. The debug circuits are
enabled by default and can only be disabled in firmware. If
disabled, the only way to re-enable them is to erase the entire
device, clear flash protection, and reprogram the device with the
new firmware that enables debugging. In addition, it is possible
to use the debug pins as GPIO too. The device has four break-
points and two watchpoints for effective debugging.
Flash
The device has a 256-KB flash memory with a flash accelerator,
tightly coupled to the CPU to improve average access times from
flash. The flash is designed to deliver 1-wait-state (WS) access
time at 48 MHz and with 0-WS access time at 24 MHz. The flash
accelerator delivers 85% of single-cycle SRAM access
performance on average. Part of the flash can be used to
emulate EEPROM operation, if required.
During flash erase and programming operations (the maximum
erase and program time is 20 ms per row), the IMO will be set to
48 MHz for the duration of the operation. This also applies to the
emulated EEPROM. System design must take this into account
because peripherals operating from different IMO frequencies
will be affected. If it is critical that peripherals continue to operate
with no change during flash programming, always set the IMO to
48 MHz and derive the peripheral clocks by dividing down from
this frequency.
SRAM
The low-power 32-KB SRAM memory retains its contents even
in Hibernate mode.
ROM
The 8-KB supervisory ROM contains a library of executable
functions for flash programming. These functions are accessed
through supervisory calls (SVC) and enable in-system
programming of the flash memory.
DMA
DMA controller provides DataWrite (DW) and Direct Memory
Access (DMA). The DMA controller has following features
■
Supports up to 8 DMA channels with two independent
descriptors per channel
■
Four levels of priority for each channel
■
Byte, half-word (2 bytes), and word (4 bytes) transfers
■
Three modes of operation supported for each channel
■
Configurable interrupt generation
■
Output trigger on completion of transfer (transfer sizes up to
65536 data elements)
Document Number: 001-95464 Rev. *J
BLE Subsystem
The BLE subsystem consists of the link layer engine and
physical layer. The link layer engine supports both master and
slave roles. The link layer engine implements time-critical
functions such as encryption in the hardware to reduce the
power consumption, and provides minimal processor
intervention and a high performance. The key protocol elements,
such as host control interface (HCI) and link control, are
implemented in firmware. The direct test mode (DTM) is included
to test the radio performance using a standard Bluetooth tester.
The physical layer consists of a modem and an RF transceiver
that transmits and receives BLE packets at the rate of 1 Mbps
over the 2.4-GHz ISM band. In the transmit direction, this block
performs GFSK modulation and then converts the digital
baseband signal of these BLE packets into radio frequency
before transmitting them to air through an antenna. In the receive
direction, this block converts an RF signal from the antenna to a
digital bit stream after performing GFSK demodulation.
The RF transceiver contains an integrated balun, which provides
a single-ended RF port pin to drive a 50-Ω antenna terminal
through a pi-matching network. The output power is
programmable from –18 dBm to +3 dBm to optimize the current
consumption for different applications.
The Bluetooth Low Energy protocol stack uses the BLE
subsystem and provides the following features:
■
Link Layer (LL)
❐
Master and Slave roles
❐
128-bit AES engine
❐
Encryption
❐
Low-duty-cycle advertising
❐
LE Ping
❐
LE Data Packet Length Extension (Bluetooth 4.2 feature)
❐
Link Layer Privacy (with extended scanning filter policy)
(Bluetooth 4.2 feature)
■
Bluetooth Low Energy 4.2 single-mode protocol stack with
logical link control and adaptation protocol (L2CAP), attribute
(ATT), and security manager (SM) protocols
■
Master and slave roles
■
API access to generic attribute profile (GATT), generic access
profile (GAP), and L2CAP
■
L2CAP connection-oriented channel
■
GAP features
❐
Broadcaster, Observer, Peripheral, and Central roles
❐
Security mode 1: Level 1, 2, 3, and 4
❐
Security mode 2: Level 1 and 2
❐
User-defined advertising data
❐
Multiple-bond support
■
GATT features
❐
GATT client and server
❐
Supports GATT subprocedures
❐
32-bit universally unique identifiers (UUID)
■
Security Manager (SM)
❐
LE Secure Connections (Bluetooth 4.2 feature)
❐
Pairing methods: Just Works, Passkey Entry, Out of Band,
and Numeric Comparison
❐
Authenticated man-in-the-middle (MITM) protection and data
signing
■
Supports all SIG-adopted BLE profiles
Page 5 of 44
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