570PAC000173DG datasheet, PDF - EEWORLD Datasheet

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570PAC000173DG: Descriptionprogrammable oscillators prgrmmbl XO 8 pin 0.3ps RS jtr (ncnr); CategoryPassive components; File Size420KB，37 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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570PAC000173DG Overview

programmable oscillators prgrmmbl XO 8 pin 0.3ps RS jtr (ncnr)

570PAC000173DG Parametric

Parameter Name	Attribute value
Manufacture	Silicon Laboratories
Product Category	Programmable Oscillators
RoHS	Yes
Package / Case	7 mm x 5 mm
Frequency	12.288 MHz
Frequency Stability	50 PPM
Supply Voltage	3.3 V
Termination Style	SMD/SMT
Dimensions	5 mm W x 7 mm L x 1.65 mm H
Mounting Style	SMD/SMT
Produc	XO
Unit Weigh	186.030 mg

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Si 5 7 0 / S i 5 7 1

10 MH

Features

Any programmable output



frequencies from 10 to 945 MHz and

select frequencies to 1.4 GHz



C serial interface



3rd generation DSPLL

with superior



jitter performance



3x better frequency stability than



SAW-based oscillators



1.4 G H

C P

ROGRAMMABLE

XO/VCXO

Internal fixed crystal frequency

ensures high reliability and low

aging

Available LVPECL, CMOS,

LVDS, and CML outputs

Industry-standard 5x7 mm

package

Pb-free/RoHS-compliant



1.8, 2.5, or 3.3 V supply

Si5602

Applications



Ordering Information:

High performance

instrumentation



Low-jitter clock generation



Optical modules



Clock and data recovery



SONET/SDH

xDSL

10 GbE LAN/WAN

ATE

See page 32.

Pin Assignments:

See page 31.

(Top View)

SDA

GND

SCL

CLK–

CLK+

Description

The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL

circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are user-

programmable to any output frequency from 10 to 945 MHz and select frequencies

to 1400 MHz with <1 ppb resolution. The device is programmed via an I

C serial

interface. Unlike traditional XO/VCXOs where a different crystal is required for

each output frequency, the Si57x uses one fixed-frequency crystal and a DSPLL

clock synthesis IC to provide any-frequency operation. This IC-based approach

allows the crystal resonator to provide exceptional frequency stability and

reliability. In addition, DSPLL clock synthesis provides superior supply noise

rejection, simplifying the task of generating low-jitter clocks in noisy environments

typically found in communication systems.

Functional Block Diagram

CLK-

CLK+

Si570

SDA

Fixed

Frequency

10-1400 MHz



DSPLL Clock

Synthesis

SCL

CLK–

CLK+

SDA

GND

Si571 only

ADC

GND

Si571

Si570/Si571

Rev. 1.5 4/14

Si570/Si571

ABLE

Section

ONTENTS

Page

1. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1. Programming a New Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2. Si570 Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3. Si570 Troubleshooting FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4. Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5. Si570 (XO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6. Si571 (VCXO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8. Si57x Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

9. Outline Diagram and Suggested Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10. 8-Pin PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Rev. 1.5

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