570BCC000148DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> 570BCC000148DG

570BCC000148DG: Descriptionprogrammable oscillators progrmable XO 8 pin 0.3ps RS jtr (ncnr); CategoryPassive components; File Size585KB，36 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

570BCC000148DG Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	570BCC000148DG	-	-	View	Buy Now

570BCC000148DG Overview

programmable oscillators progrmable XO 8 pin 0.3ps RS jtr (ncnr)

570BCC000148DG Parametric

Parameter Name	Attribute value
Manufacture	Silicon Laboratories
Product Category	Programmable Oscillators
RoHS	Yes

Preview

Download Datasheet

View All

Si 5 7 0 / S i 5 7 1

10 MH

Features



1.4 G H

C P

ROGRAMMABLE

XO/VCXO

Any programmable output



frequencies from 10 to 945 MHz and

select frequencies to 1.4 GHz



C serial interface



3rd generation DSPLL

with superior



jitter performance



3x better frequency stability than



SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available LVPECL, CMOS,

LVDS, and CML outputs

Industry-standard 5x7 mm

package

Pb-free/RoHS-compliant



1.8, 2.5, or 3.3 V supply

Si5602

Applications



Ordering Information:



SONET/SDH

xDSL

10 GbE LAN/WAN

ATE

High performance

instrumentation



Low-jitter clock generation



Optical modules



Clock and data recovery

See page 31.

Pin Assignments:

See page 30.

(Top View)

SDA

Description

The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL

circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are user-

programmable to any output frequency from 10 to 945 MHz and select frequencies

to 1400 MHz with <1 ppb resolution. The device is programmed via an I

C serial

interface. Unlike traditional XO/VCXOs where a different crystal is required for

each output frequency, the Si57x uses one fixed-frequency crystal and a DSPLL

clock synthesis IC to provide any-frequency operation. This IC-based approach

allows the crystal resonator to provide exceptional frequency stability and

reliability. In addition, DSPLL clock synthesis provides superior supply noise

rejection, simplifying the task of generating low-jitter clocks in noisy environments

typically found in communication systems.

CLK–

GND

SCL

CLK+

Functional Block Diagram

CLK-

CLK+

Si570

SDA

Fixed

Frequency

10-1400 MHz



DSPLL Clock

Synthesis

SDA

SCL

CLK–

Si571 only

ADC

GND

SCL

CLK+

GND

Si571

Si570/Si571

Rev. 1.6 6/18

Recommended Resources

Autotransformer schematic diagram

The third delay circuit using 555 time base integrated circuit

pH sensor measurement circuit

Digital conversion circuit for measuring angle using angular velocity signal

Computer motherboard circuit diagram 440GX_12

1. Power supply circuit diagram of AOC CM-312 color display

How to obtain core coins?: I haven't been here for a long time, and suddenly I discovered that there is a new change. Is it necessary to download core coins to increase the popularity of visits? Are there any other reasons?...; lwz3968 MCU

Understanding common mode and differential mode: [size=4] What we need is the entire meaningful "input signal", and we need to regard the two input terminals as a "whole". [/size] [size=4] Just like in junior high school, plane coordinates need to b...; Aguilera Analogue and Mixed Signal

I would like to ask you a question about calculating the sampling rate!: When I use AD12, the register settings are as follows:ADC12CTL0 = MSC+REFON+REF2_5V+SHT0_8+SHT1_8;ADC12CTL1 = (0 What is the sampling rate of my program? I don't know how to calculate it, which expert...; qscft Microcontroller MCU

The electric baking pan is in place, thanks to the forum and Renesas: Thanks to the forum activities and the prizes from Renesas, I can now make pancakes and grill chicken wings. It's a great blessing for a foodie, haha....; 人民币的幻想 Renesas Electronics MCUs

IAR, it's really troublesome to change it again and again: IAR compiles STM32's M3. In earlier versions, you need to use the core_cm3 file, but it is no longer used after version 6. If a project that was successfully compiled using version 6 is now compiled u...; dontium MCU

From ASIC prototype verification to high-end FPGA: List of major high-end ASIC prototype verification products in the industryThis table verifies the previous preliminary judgment that in the high-end field, Xilinx has an absolute market position, whe...; loodnew FPGA/CPLD

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components