8T49N222B-100NLGI datasheet, PDF

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8T49N222B-100NLGI: Descriptionclock generators & support products femto NG clock generator; Categorysemiconductor Other integrated circuit (IC); File Size683KB，40 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/; Environmental Compliance

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clock generators & support products femto NG clock generator

8T49N222B-100NLGI Parametric

Parameter Name	Attribute value
Manufacture	IDT (Integrated Device Technology)
Product Category	Clock Generators & Support Products
RoHS	Yes
Type	Clock Translators
Max Input Freq	710 MHz
Max Output Freq	1200 MHz
Number of Outputs	2
Duty Cycle - Max	55 %
Operating Supply Voltage	2.5 V, 3.3 V
Operating Supply Curre	358 mA
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	VFQFPN-48
Minimum Operating Temperature	- 40 C
Output Type	LVPECL, LVDS
Packaging	Tube
Factory Pack Quantity	260

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DATA SHEET

FemtoClock® NG Universal Frequency

Translator

Features

•

IDT8T49N222I

General Description

The IDT8T49N222I is a highly flexible FemtoClock® NG general

purpose, low phase noise Frequency Translator / Synthesizer with

alarm and monitoring functions suitable for networking and

communications applications. It is able to generate any output

frequency in the 7.29MHz to 833.33MHz range and most output

frequencies in the 925MHz to 1200MHz range (see Table 3A for

details). A wide range of input reference clocks and a range of

low-cost fundamental mode crystal frequencies may be used as the

source for the output frequency.

The IDT8T49N222I has three operating modes to support a very

broad spectrum of applications:

1) Frequency Synthesizer

Fourth generation FemtoClock® NG technology

Universal Frequency Translator

•

Zero ppm frequency translation

Two outputs, individually programmable as LVPECL or LVDS

•

Outputs may be individually set to use 2.5V or 3.3V output

levels

•

Individually programmable output frequencies: 7.29MHz up to

1200MHz

Two differential inputs support the following input types:

LVPECL, LVDS, LVHSTL, HCSL

•

Input frequency range: 8kHz to 710MHz

•

Hitless switching between inputs

Crystal input frequency range: 16MHz to 40MHz

•

Holdover support in the event both inputs fail

One factory-set register configuration for power-up default state

•

Configurations customized via One-Time Programmable ROM

•

Settings may be overwritten after power-up via I

•

C Serial interface for register programming

RMS phase jitter at 156.25MHz, using a 40MHz crystal

(12kHz - 20MHz): 507fs (typical), Low Bandwidth Mode (FracN)

Supports ITU-T G.8262 Synchronous Ethernet equipment slave

clocks (EEC option 1 and 2)

Output supply voltage modes:

CCA

CCOx

3.3V/3.3V/3.3V

3.3V/3.3V/2.5V (LVPECL only)

2.5V/2.5V/2.5V

-40°C to 85°C ambient operating temperature

Available in lead-free (RoHS 6) package

•

Synthesizes output frequencies from a 16MHz - 40MHz

fundamental mode crystal.

Fractional feedback division is used, so there are no

requirements for any specific crystal frequency to produce the

desired output frequency with a high degree of accuracy.

Applications: PCI Express, Computing, General Purpose

Translates any input clock in the 16MHz - 710MHz frequency

range into any supported output frequency.

This mode has a high PLL loop bandwidth in order to track input

reference changes, such as Spread-Spectrum Clock

modulation, so it will not attenuate much jitter on the input

reference.

Applications: Networking & Communications.

Translates any input clock in the 8kHz –710MHz frequency

range into any supported output frequency.

This mode supports PLL loop bandwidths in the 10Hz - 580Hz

range and makes use of an external crystal to provide

significant jitter attenuation.

•

2) High-Bandwidth Frequency Translator

•

3) Low-Bandwidth Frequency Translator

•

This device provides a factory-programmed default power-up

configuration burned into One-Time Programmable (OTP) memory.

The configuration is specified by the customer and is programmed by

IDT during the final test phase from an on-hand stock of blank

devices.

To implement other configurations, these power-up default settings

can be overwritten after power-up using the I

C interface and the

device can be completely reconfigured. However, these settings

would have to be written every time the device powers-up.

Pin Assignment

nQ0

OE0

LOCK_IND

CCO0

nQ1

CCO1

S_AO

S_A1

Reserved

SCLK

SDATA

PLL_BYPASS

CLK_ACTIVE

LF0

LF1

CCA

HOLDOVER

CLK0BAD

CLK1BAD

XTALBAD

36 35 34 33 32 31 30

29 28 27 26 25

IDT8T49N222I

48 Lead VFQFN

7.0mm x 7.0mm x 0.925mm,

package body

NL Package

Top View

1 2

4 5 6 7

8 9

10 11 12

XTAL_OUT

CLK_SEL

CLK0

nCLK0

XTAL_IN

CLK1

nCLK1

IDT8T49N222BNLGI REVISION A MAY 13, 2013

OE1

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