Synchronous Equipment Timing Source
for Synchronous Ethernet and Optical
Transport Network
Advance Datasheet
8A34046
Overview
The 8A34046 Synchronous Equipment Timing Source (SETS) for
Synchronous Ethernet (SyncE) and Optical Transport Network
(OTN) is a highly integrated timing device with four Digital PLL
(DPLL) channels and four Digitally Controlled Oscillator (DCO)
channels. The DPLLs can lock to external references or operate in
free run, and can be configured as DCOs. Each of the DCOs can
be synchronized by any of the DPLLs or they can operate in free
run. The DCOs can alternatively be controlled by an external
algorithm for Optical Transport Network (OTN) applications.
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12 differential / 24 LVCMOS outputs
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Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS)
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Jitter below 150fs RMS (10kHz to 20MHz)
•
Supports LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL,
and HSTL output modes
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Differential output swing is selectable: 400mV / 650mV /
800mV / 910mV
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Independent output voltages of 3.3V, 2.5V, or 1.8V
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LVCMOS additionally supports 1.5V or 1.2V swings
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The clock phase of each output is individually programmable
in 1ns to 2ns steps with a total range of ±180°
Typical Applications
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Core and access IP switches / routers
Synchronous Ethernet equipment
10Gb, 40Gb, and 100Gb Ethernet interfaces
Wireless infrastructure for 4.5G and 5G network equipment
OTN muxponders and line cards
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4 differential / 8 single-ended clock inputs
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Supports frequencies from 1kHz to 1GHz
Any input can be mapped to any or all of the timing channels
Features
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Compliant with G.8262 option 1 and option 2, and G.8262.1
Supports all ITU-T G.709 frequencies
Meets OTN jitter and wander requirements per ITU-T G.8251
Four independent timing channels
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Each can act as a frequency synthesizer, jitter attenuator,
Digitally Controlled Oscillator (DCO), or Digital Phase Lock
Loop (DPLL)
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DPLL Digital Loop Filters (DLFs) are programmable with
cut-off frequencies from 0.1Hz to 12kHz
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Generates output frequencies that are independent of input
frequencies via a Fractional Output Divider (FOD)
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Each FOD supports output phase tuning with 50ps
resolution
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Four Satellite DCO channels
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Each can act as a frequency translator connected to either
DPLL channel or as an independent frequency synthesizer
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Generates output frequencies that are independent of input
frequencies via a Fractional Output Divider (FOD)
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Each FOD supports output phase tuning with 50ps
resolution
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Can configure itself automatically after reset via:
Redundant inputs frequency independent of each other
Any input can be designated as external frame/sync pulse of
EPPS (even pulse per second), 1PPS (Pulse per Second),
5PPS, 10PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz
associated with a selectable reference clock input
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Per-input programmable phase offset of up to ±1.638s in
50ps steps
Reference monitors qualify/disqualify references depending on
LOS, activity, frequency monitoring, and/or LOS input pins
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Loss of Signal (LOS) input pins (via GPIOs) can be assigned
to any input clock reference
Automatic reference selection state machines select the active
reference for each DPLL based on the reference monitors,
priority tables, revertive / non-revertive, and other
programmable settings
System APLL operates from fundamental-mode crystal: 25MHz
to 54MHz or from a crystal oscillator
System DPLL accepts an XO, TCXO, or OCXO operating at
virtually any frequency from 1MHz to 150MHz
DPLLs can be configured as DCOs to synthesize clocks under
the control of an external algorithm
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DCOs generate with frequency resolution less than
1.11 × 10
-16
Supports 1MHz I
2
C or 50MHz SPI serial processor ports
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Internal Customer-programmable One-Time Programmable
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(OTP) memory with up to 16 different configurations
Standard external I
2
C EEPROM if serial port in I
2
C mode
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1149.1 JTAG Boundary Scan
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10 × 10 mm 72-QFN package
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8A34046 Advance Datasheet
Block Diagram
Figure 1. Block Diagram
XO_DPLL
(Optional)
System
DPLL
FOD
To FODs
OSCI OSCO
Osc
System
APLL
Div
Div
Div
Div
Div
Div
Div
Div
Div
Out
Out
Out
Out
Out
Out
Out
Out
Out
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Combo Bus
(Frequency Data)
DPLL /
DCO_0
Reference
Monitors
Reference
Switching
State
Machines
DPLL /
DCO_1
DPLL /
DCO_2
DPLL /
DCO_3
DCO_4
FOD
CLK0
CLK1
CLK2
CLK3
FOD
FOD
FOD
FOD
DCO_5
FOD
Div
Out
Q9
DCO_6
FOD
Div
Out
Q10
DCO_7
Status and Configuration
Registers
I
2
C Master
FOD
Div
Out
Q11
OTP
SPI/I
2
C
GPIO / JTAG
Description
The 8A34046 Synchronous Equipment Timing Source (SETS) for SyncE and OTN is a highly integrated timing device with four Digital
PLL (DPLL) channels and four Digitally Controlled Oscillator (DCO) channels. The DPLLs can lock to external references or operate in
free run, and can be configured as DCOs. Each of the DCOs can be synchronized by any of the DPLLs or they can operate in free run.
The DCOs can alternatively be controlled by an external algorithm for Optical Transport Network (OTN) applications.
The 8A34046 supports precise control of input-to-input, input-to-output, and output-to-output phase skew. The device outputs low-jitter
clocks that can directly synchronize interfaces such as 100GBASE-R, 40GBASE-R, 10GBASE-R, and 10GBASE-W and lower-rate
Ethernet interfaces, as well as SONET/SDH and PDH interfaces.
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8A34046 Advance Datasheet
The internal System APLL must be supplied with a low phase noise reference clock with frequency between 25MHz and 54MHz. The
output of the System APLL is used for clock synthesis by all of the Fractional Output Dividers (FODs) in the device. The System APLL
reference can come from an external crystal oscillator connected to the OSCI pin or from an internal oscillator that uses a crystal
connected between the OSCI and OSCO pins.
The System DPLL generates an internal system clock that is used by the reference monitors and other digital circuitry in the device. If the
reference provided to the System APLL meets the stability and accuracy requirements of the intended application then the System DPLL
can free run and a System DPLL reference is not required. Alternatively, the System DPLL can be locked to an external reference that
meets the stability and accuracy requirements of the intended application. The System DPLL can accept a reference from the XO_DPLL
pin or via the reference selection mux.
The frequency accuracy/stability of the internal system clock determines the frequency accuracy/stability of the DPLLs in Free-Run mode
and in Holdover mode, and also affects the wander generation of the DPLLs in Locked and DCO modes. When provided with a suitably
stable and accurate system clock, the DPLLs meet the frequency accuracy, pull-in, hold-in, pull-out, noise generation, noise tolerance,
transient response, and holdover performance requirements of ITU-T G.8262 synchronous Ethernet Equipment Clock (EEC) options 1
and 2.
The 8A34046 accepts up to 2 four differential reference inputs and up to 4 eight single-ended reference inputs that can operate at
common GNSS, Ethernet, SONET/SDH, PDH frequencies, and any input frequency from 1kHz to 1GHz (250MHz in single-ended mode).
The references are continually monitored for loss of signal and for frequency offset per user programmed thresholds. All of the references
are available to all the DPLLs. The active reference for each DPLL is determined by forced selection or by automatic selection based on
user programmed priorities, locking allowances, reference monitors, revertive and non-revertive settings, and LOS inputs.
The 8A34046 provides four independent Digital Phase Lock Loops (DPLLs) consisting of a Phase Frequency Detector (PFD), a Low Pass
Filter (LPF), and a Digitally Controlled Oscillator (DCO). The DPLL architecture allows external processors to access the control loop at
several points to monitor and control the loop. A processor can directly control the DCOs; and it can implement a proprietary filter and
control algorithm to replace the internal LPF.
The 8A34046 can accept a clock reference and an associated frame pulse or sync signal as a pair. The DPLLs can lock to the clock
reference and align the sync and clock outputs with the paired sync/frame input. The device allows any of the reference inputs to be
configured as sync inputs that can be associated with any of the other reference inputs. The input sync signals can have a frequency of
1PPS (Pulse per Second), EPPS (even pulse per second), 5PPS, 10PPS, 50Hz, 100Hz, 1kHz, 2kHz, 4kHz, and 8 kHz. This feature
enables any DPLL to phase align its frame sync and clock outputs with a sync input without the need to use a low bandwidth setting to
lock directly to the sync input.
The DPLLs support four primary operating modes: Free-Run, Locked, Holdover, and DCO. In Free-Run mode the DPLLs synthesize
clocks based on the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth, and the
long-term output frequency accuracy is the same as the long-term frequency accuracy of the selected input reference. In Holdover mode,
the DPLL uses frequency data acquired while in Locked mode to generate accurate frequencies when input references are not available.
In DCO mode, the DPLL control loop is opened and the DCO can be controlled by an external algorithm via serial port to dynamically
adjust the output clock frequency.
The DPLLs can be configured with a range of selectable filtering bandwidths. Bandwidths in the range of 0.1Hz to 10Hz can be used for
G.8262/G.813, Telcordia GR-253-CORE S3, or SMC applications. Bandwidths above 10Hz can be used in jitter attenuation and rate
conversion applications.
In addition, there are four Satellite channels that can operate either as independent frequency synthesizers, as DCOs, or as frequency
translators. In synthesizer mode, a channel uses a Fractional Output Divider (FOD) clocked from the System APLL to generate any
desired output frequency. In DCO mode, the channel can be controlled by an external algorithm via serial port to dynamically adjust the
output clock frequency. In frequency translation mode, the FOD will receive frequency-tracking information from any DPLL channel,
tracking the input that DPLL channel is locked to, but with an output frequency that is a fractional ratio to the DPLL it is tracking.
All of the channels within the 8A34046 derive their output frequencies from the same System APLL clock, and therefore, the control
words used to tune the DCOs are interchangeable.
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8A34046 Advance Datasheet
The 8A34046 generates up to 12 differential output clocks at any frequency from 0.5Hz to 1GHz. The differential outputs can support
LVPECL, LVDS, HCSL, and CML. It generates up to 24 single-ended clocks with frequencies from 0.5Hz to 250MHz. LVCMOS output
supports 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V. Each output stage can be independently configured.
Clocks generated by the 8A34046 have jitter below 150fs RMS (10kHz to 20MHz), and therefore are suitable for serial 100GBASE-R,
40GBASE-R, and lower rate interfaces.
All control and status registers are accessed through the I
2
C / SPI slave microprocessor interface. The SPI interface mode supports high
clock rates (up to 50MHz). For configuring the DPLLs, the 8A34046 has an internal customer-programmable OTP memory with up to 16
different configurations. If the serial port is configured in I
2
C mode, then the 8A34046 can become master on this I
2
C bus and read
configuration data from a standard I
2
C EEPROM that shares the I
2
C bus. If the serial port is configured in SPI mode then this capability is
unavailable.
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8A34046 Datasheet
Contents
Overview .............................................................................................................................................................................................................. 1
Typical Applications.............................................................................................................................................................................................. 1
Features ............................................................................................................................................................................................................... 1
Block Diagram ...................................................................................................................................................................................................... 2
Description ........................................................................................................................................................................................................... 2
Pin Assignment .................................................................................................................................................................................................. 10
Pin Descriptions and Pin Characteristics ........................................................................................................................................................... 10
Overview of the 8A3xxxx Family ........................................................................................................................................................................ 15
Functional Description........................................................................................................................................................................................ 15
Basic Functional Blocks of the 8A34046 ............................................................................................................................................................ 16
Crystal Input (OSCI / OSCO) ...................................................................................................................................................................... 16
Frequency Representation in 8A34046............................................................................................................................................. 16
System Analog PLL (APLL) ........................................................................................................................................................................ 16
Input Stage.................................................................................................................................................................................................. 17
Reference Monitoring.................................................................................................................................................................................. 19
Loss of Signal (LOS) Monitoring........................................................................................................................................................ 19
Activity ............................................................................................................................................................................................... 20
Timer ................................................................................................................................................................................................. 21
Frequency Offset Monitoring ............................................................................................................................................................. 21
Advanced Input Clock Qualification ............................................................................................................................................................ 22
Input Clock Qualification.................................................................................................................................................................... 22
Clock Reference Disqualifier through GPIO...................................................................................................................................... 22
Frame Pulse Operation............................................................................................................................................................................... 22
Sync Pulse Operation ................................................................................................................................................................................. 23
Crystal Oscillator Input (XO_DPLL) ............................................................................................................................................................ 24
Digital Phase Locked Loop (DPLL)............................................................................................................................................................. 24
Free-Run Mode ................................................................................................................................................................................. 26
Locked Mode..................................................................................................................................................................................... 26
Holdover Mode .................................................................................................................................................................................. 26
Manual Holdover Mode ..................................................................................................................................................................... 27
DPLL Input Clock Qualification and Selection............................................................................................................................................. 27
Automatic Input Clock Selection........................................................................................................................................................ 27
Manual Input Clock Selection via Register or GPIO.......................................................................................................................... 27
Slave or GPIO Slave Selection.......................................................................................................................................................... 27
DPLL Switchover Management................................................................................................................................................................... 28
Revertive and Non-Revertive Switching............................................................................................................................................ 28
Hitless Reference Switching.............................................................................................................................................................. 28
Phase Slope Limiting......................................................................................................................................................................... 28
DPLL Frequency Offset Limit Setting ................................................................................................................................................ 28
DPLL Fast Lock Operation.......................................................................................................................................................................... 29
Satellite Channel......................................................................................................................................................................................... 30
Steerable Fractional Output Divider (FOD)................................................................................................................................................. 30
FOD Multiplexing and Output Stages.......................................................................................................................................................... 31
Integer Output Divider ....................................................................................................................................................................... 32
Output Duty Cycle Adjustment .......................................................................................................................................................... 33
Output Coarse Phase Adjustment..................................................................................................................................................... 33
Output Buffer ..................................................................................................................................................................................... 34
General Purpose Input/Outputs (GPIOs) .................................................................................................................................................... 35
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