54173 DM54173 DM74173 TRI-STATE Quad D Registers
June 1989
54173 DM54173 DM74173
TRI-STATE Quad D Registers
General Description
These four-bit registers contain D-type flip-flops with totem-
pole TRI-STATE outputs capable of driving highly capaci-
tive or low-impedance loads The high-impedance state and
increased high-logic-level drive provide these flip-flops with
the capability of driving the bus lines in a bus-organized sys-
tem without need for interface or pull-up components
Gated enable inputs are provided for controlling the entry of
data into the flip-flops When both data-enable inputs are
low data at the D inputs are loaded into their respective flip-
flops on the next positive transition of the buffered clock
input Gate output control inputs are also provided When
both are low the normal logic states of the four outputs are
available for driving the loads or bus lines The outputs are
disabled independently from the level of the clock by a high
logic level at either output control input The outputs then
present a high impedance and neither load nor drive the bus
line Detailed operation is given in the function table
To minimize the possibility that two outputs will attempt to
take a common bus to opposite logic levels the output con-
trol circuitry is designed so that the average output disable
times are shorter than the average output enable times
Features
Y
Y
Y
Y
Y
Y
Y
Y
TRI-STATE outputs interface directly with system bus
Gated output control lines for enabling or disabling the
outputs
Fully independent clock elminates restrictions for oper-
ating in one of two modes
Parallel load
Do nothing (hold)
For application as bus buffer registers
Typical propagation delay 18 ns
Typical frequency 30 MHz
Typical power dissipation 250 mW
Alternate Military Aerospace device (54173) is avail-
able Contact a National Semiconductor Sales Office
Distributor for specifications
Connection Diagram
Dual-In-Line Package
Function Table
Inputs
Data Enable
Clear
H
L
L
L
L
L
Clock
G1
X
L
X
X
H
X
L
L
G2
X
X
X
H
L
L
Data
D
X
X
X
X
L
H
Output
Q
L
Q
0
Q
0
Q
0
L
H
u
u
u
u
When either M or N (or both) is (are) high the output is disabled to the
high-impedance state however sequential operation of the flip-flops is
not affected
H
e
high level (steady state)
L
e
low level (steady state)
u
e
low-to-high level transition
X
e
don’t care (any input including transitions)
Q
0
e
the level of Q before the indicated steady state input conditions were
established
TL F 6556 – 1
Order Number 54173DMQB 54173FMQB
DM54173J DM54173W or DM74173N
See NS Package Number J16A N16E or W16A
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 6556
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
Input Voltage
7V
5 5V
Note
The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Operating Free Air Temperature Range
b
55 C to
a
125 C
DM54 and 54
DM74
0 C to
a
70 C
Storage Temperature Range
b
65 C to
a
150 C
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
f
CLK
t
W
t
SU
t
H
t
REL
T
A
Parameter
Min
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 4)
Pulse Width
(Note 4)
Setup Time
(Note 4)
Hold Time
(Note 4)
Clock
Clear
Enable
Data
Enable
Data
0
20
20
17
10
2
10
10
b
55
DM54173
Nom
5
Max
55
08
b
2
DM74173
Min
4 75
2
08
b
5 2
Units
Max
5 25
V
V
V
mA
mA
MHz
ns
ns
ns
ns
70
C
Nom
5
45
2
16
25
0
20
20
17
10
2
10
10
125
0
16
25
Clear Release Time (Note 4)
Free Air Operating Temperature
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
V
I
V
OH
V
OL
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
CC
Parameter
Input Clamp Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Current
Input Voltage
Max
Conditions
V
CC
e
Min I
I
e b
12 mA
V
CC
e
Min I
OH
e
Max
V
IL
e
Max V
IH
e
Min
V
CC
e
Min I
OL
e
Max
V
IH
e
Min V
IL
e
Max
V
CC
e
Max V
I
e
5 5V
V
CC
e
Max V
I
e
2 4V
V
CC
e
Max V
I
e
0 4V
V
CC
e
Max V
O
e
2 4V
V
IH
e
Min V
IL
e
Max
V
CC
e
Max V
O
e
0 4V
V
IH
e
Min V
IL
e
Max
V
CC
e
Max
(Note 2)
V
CC
e
Max (Note 3)
DM54
DM74
b
30
b
30
Min
Typ
(Note 1)
Max
b
1 5
Units
V
V
24
04
1
40
b
1 6
V
mA
mA
mA
mA
mA
mA
mA
High Level Input Current
Low Level Input Current
Off-State Output Current with High
Level Output Voltage Applied
Off-State Output Current with Low
Level Output Voltage Applied
Short Circuit
Output Current
Supply Current
40
b
40
b
70
b
70
50
72
Note 1
All typicals are at V
CC
e
5V T
A
e
25 C
Note 2
Not more than one output should be shorted at a time
Note 3
I
CC
is measured with all outputs open CLEAR grounded after a momentary connection to 4 5V N G1 G2 and all DATA inputs grounded and the CLOCK
input and M input at 4 5V
Note 4
T
A
e
25 C and V
CC
e
5V
2
京公网安备 11010802033920号
EEWORLD
