EEWORLDEEWORLDEEWORLD

Part Number

Search

MT47H128M8B7-25EIT

Description
DDR DRAM, 128MX8, 0.4ns, CMOS, PBGA68,
Categorystorage    storage   
File Size8MB,137 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance
Download Datasheet Parametric View All

MT47H128M8B7-25EIT Overview

DDR DRAM, 128MX8, 0.4ns, CMOS, PBGA68,

MT47H128M8B7-25EIT Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid106531337
package instructionFBGA, BGA68,9X19,32
Reach Compliance Codecompliant
ECCN codeEAR99
YTEOL4.75
Maximum access time0.4 ns
Maximum clock frequency (fCLK)400 MHz
I/O typeCOMMON
interleaved burst length4,8
JESD-30 codeR-PBGA-B68
memory density1073741824 bit
Memory IC TypeDDR2 DRAM
memory width8
Number of terminals68
word count134217728 words
character code128000000
organize128MX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeFBGA
Encapsulate equivalent codeBGA68,9X19,32
Package shapeRECTANGULAR
Package formGRID ARRAY, FINE PITCH
power supply1.8 V
Certification statusNot Qualified
refresh cycle8192
Continuous burst length4,8
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
1Gb: x4, x8, x16 DDR2 SDRAM
Features
DDR2 SDRAM
MT47H256M4 – 32 Meg x 4 x 8 banks
MT47H128M8 – 16 Meg x 8 x 8 banks
MT47H64M16 – 8 Meg x 16 x 8 banks
For the latest data sheet, refer to Micron’s Web site:
http://www.micron.com/ddr2
Features
RoHS compliant
V
DD
= +1.8V ±0.1V, V
DD
Q = +1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency – 1
t
CK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength
64ms, 8,192-cycle refresh
On-die termination (ODT)
Industrial temperature (IT) option
Supports JEDEC clock jitter specification
Options
• Configuration
256 Meg x 4 (32 Meg x 4 x 8 banks )
128 Meg x 8 (16 Meg x 8 x 8 banks)
64 Meg x 16 (8 Meg x 16 x 8 banks)
• FBGA package (lead-free)
92-ball FBGA (11mm x 19mm) (:A)
84-ball FBGA (10mm x 16.5mm) (:D)
68-ball FBGA (10mm x 16.5mm) (:D)
• Timing – cycle time
5.0ns @ CL = 3 (DDR2-400)
3.75ns @ CL = 4 (DDR2-533)
3.0ns @ CL = 5 (DDR2-667)
3.0ns @ CL = 4 (DDR2-667)
2.5ns @ CL = 6 (DDR2-800)
2.5ns @ CL = 5 (DDR2-800)
• Self refresh
Standard
Low-power
• Operating temperature
Commercial (0°C
T
C
85°C)
Industrial (–40°C
T
C
95°C; –40°C
T
A
85°C)
• Revision
Marking
256M4
128M8
64M16
BT
B7
B7
-5E
-37E
-3
-3E
-25
-25E
None
L
None
IT
:A/:D
Table 1:
Architecture
Configuration Addressing
256 Meg x 4 128 Meg x 8 64 Meg x 16
8 Meg x 16
x 8 banks
8K
8K (A0–A12)
8 (BA0–BA2)
1K (A0–A9)
Table 2:
Key Timing Parameters
RC
(ns)
55
55
55
54
55
55
t
32 Meg x 4
16 Meg x 4
x 8 banks
x 8 banks
8K
8K
Refresh Count
16K (A0–A13) 16K (A0–A13)
Row Addr.
8 (BA0–BA2) 8 (BA0–BA2)
Bank Addr.
Column Addr. 2K (A0–A9, A11) 1K (A0–A9)
Configuration
Data Rate (MHz)
t
Speed
RCD
t
RP
Grade CL = 3 CL = 4 CL = 5 CL = 6 (ns) (ns)
-5E
-37E
-3
-3E
-25
-25E
400
400
400
N/A
N/A
N/A
400
533
533
667
N/A
533
N/A
N/A
667
667
667
800
N/A
N/A
N/A
N/A
800
N/A
15
15
15
12
15
12.5
15
15
15
12
15
12.5
Note: CL = CAS latency.
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbbDDR2_1.fm - Rev. K 4/06 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2474  1269  367  2356  138  50  26  8  48  3 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号