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UPD4442361GF-C85Y

Description
Cache SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100
Categorystorage    storage   
File Size234KB,24 Pages
ManufacturerNEC Electronics
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UPD4442361GF-C85Y Overview

Cache SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100

UPD4442361GF-C85Y Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Objectid1912823552
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time8.5 ns
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
memory density4718592 bit
Memory IC TypeCACHE SRAM
memory width36
Number of functions1
Number of terminals100
word count131072 words
character code128000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize128KX36
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height1.7 mm
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
width14 mm
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
4M-BIT CMOS SYNCHRONOUS FAST SRAM
FLOW THROUGH OPERATION
Description
The
µ
PD4442161-Y is a 262,144-word by 16-bit, the
µ
PD4442181-Y is a 262,144-word by 18-bit, the
µ
PD4442321-Y
is a 131,072-word by 32-bit and the
µ
PD4442361-Y is a 131,072-word by 36-bit synchronous static RAM fabricated
with advanced CMOS technology using Full-CMOS six-transistor memory cell.
The
µ
PD4442161-Y,
µ
PD4442181-Y,
µ
PD4442321-Y and
µ
PD4442361-Y integrate unique synchronous peripheral
circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive
edge of the single clock input (CLK).
The
µ
PD4442161-Y,
µ
PD4442181-Y,
µ
PD4442321-Y and
µ
PD4442361-Y are suitable for applications which require
synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer
memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).
In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal
operation.
The
µ
PD4442161-Y,
µ
PD4442181-Y,
µ
PD4442321-Y and
µ
PD4442361-Y are packaged in 100-pin PLASTIC LQFP
with a 1.4 mm package thickness for high density and low capacitive loading.
Features
3.3 V (A version) or 2.5 V (C version) Core Supply
Synchronous operation
Extended operating temperature (T
A
= –40 to +85
°C)
Internally self-timed write control
Burst read / write : Interleaved burst and linear burst sequence
Fully registered inputs for flow through operation
All registers triggered off positive clock edge
3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs
Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)
Asynchronous output enable : /G
Burst sequence selectable : MODE
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
Separate byte write enable : /BW1 - /BW4 (
µ
PD4442321-Y,
µ
PD4442361-Y), /BW1 - /BW2 (
µ
PD4442161-Y,
µ
PD4442181-Y), /BWE
Global write enable : /GW
Three chip enables for easy depth expansion
Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M15502EJ1V0DS00 (1st edition)
Date Published May 2001 NS CP(K)
Printed in Japan
©
2001
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