DEVELOPMENT KIT
(Info
Click here)
•
2.4 GHz Spread Spectrum Transceiver Module
•
Small Size, Light Weight, Built-In Antenna
•
Sleep Current less than 3 µA
•
FCC, Canadian IC and ETSI Certified for Unlicensed Operation
The LPR2430ERA 2.4 GHz transceiver module is a low cost, high-power solution for
peer-to-peer, point-to-point and point-to-multipoint wireless designs. LPR2430ERA
modules provide the flexibility and versatility to serve applications ranging from cable
replacements to sensor networks. Based on the IEEE 802.15.4 wireless standard,
the LPR2430ERA module is easy to integrate, requires no external antenna, and pro-
vides robust wireless communications in applications where mesh network operation
is not required. The LPR2430ERA includes CNL V2.0 Network Layer firmware which
features a flexible and simple-to-use Application Programming Interface.
LPR2430ERA Absolute Maximum Ratings
Rating
All Input/Output Pins
Non-Operating Ambient Temperature Range
LPR2430ERA Electrical Characteristics
Characteristic
Operating Frequency Range
Operating Frequency Tolerance
Spread Spectrum Method
Modulation Type
Number of RF Channels
RF Data Transmission Rate
Symbol Rate Tolerance
RF Channel Spacing
Receiver Sensitivity, 10E-5 BER
Upper Adjacent Channel Rejection, +5 MHz
Lower Adjacent Channel Rejection, -5 MHz
Upper Alternate Channel Rejection, +10 MHz
Lower Alternate Channel Rejection, -10 MHz
Maximum RF Transmit Power
Transmit Power Adjustment
Optimum Antenna Impedance
Sym
Notes
Minimum
2405
-300
Value
-0.3 to +6.0
-40 to +85
Units
V
o
LPR2430ERA
High Power
802.15.4 Module
with Chip
Antenna
C
Shown with Shield Removed
Typical
Maximum
2475
300
Units
MHz
kHz
Direct Sequence
O-QPSK
15
250
120
5
-95
41
30
55
53
18
20
50
kb/s
ppm
MHz
dBm
dB
dB
dB
dB
dBm
dB
W
www.RFM.com E-mail: info@rfm.com
©2009 by RF Monolithics, Inc.
Page 1 of 5
LPR2430ERA - 06/19/09
LPR2430ERA Electrical Characteristics
Characteristic
ADC Input Range
ADC Input Resolution
ADC Input Impedance
PWM Output Resolution*
UART Baud Rates
Digital I/O:
Logic Low Input Level
Logic High Input Level
Logic Input Internal Pull-up/Pull-down Resistor
GPIO3 Logic Low Sink Current
Power Supply Voltage Range
Power Supply Voltage Ripple
Receive Mode Current
Transmit Mode Current
Sleep Mode Current
Operating Temperature Range
-40
33
130
3
85
V
CC
+3.3
-0.3
2.8
20
20
+5.5
10
0.5
3.6
V
V
KW
mA
Vdc
mV
P-P
mA
mA
µA
o
Sym
Notes
Minimum
0
Typical
Maximum
3.3
Units
V
bits
MW
11
55
8
16
bits
kb/s
1.2, 2.4, 4.8, 9.6 (default), 19.2,
28.8, 38.4, 57.6, 76.8, 115.2
C
*PWM0 has 8-bit resolution, PWM1 has 16-bit resolution. Built-in PWM output filters suppress ripple to 7 bits. Additional filtering
can be added externally.
CAUTION: Electrostatic Sensitive Device. Observe precautions when handling.
www.RFM.com E-mail: info@rfm.com
©2009 by RF Monolithics, Inc.
Page 2 of 5
LPR2430ERA - 06/19/09
L P R 2 4 3 0 E R A B lo c k D ia g r a m
+ 3 .3 V
G N D
1
A C T IV IT Y
3 2 .7 6 8 k H z
2
3
3 2 M H z
L IN K
G P IO 0 (A D C _ R E F )
4
5
6
7
8
9
R A D IO _ T X D
R A D IO _ R X D
/H O S T _ C T S (G P IO 4 )
/H O S T _ R T S (G P IO 5 )
P W M 0
G P IO 2 (P W M 1 )
G P IO 1
G P IO 3 (R S 4 8 5 _ E N )
P W M 1 (G P IO 2 )
V C C
G N D
S w itc h
P W R
T X /R X
C o m b in e r
F ilte r
C C
8 0 2
R a d
M ic r o c
2 4
.1
io
o n
3 0
5 .4
a n d
tr o lle r
T /R
T /R
F ilte r
R F IO
P R E
2 8
1 0
1 1
1 2
1 3
1 4
1 5
+ 3 .3 V
F ilte r
R e g
3 0
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
N C
N C
/R E S E T
R S D V
R S D V
R S D V
R S D V
G N D
A D C 2
A D C 1
A D C _ V D D
A D C 0
Figure 1
LPR2430ERA Hardware
The major hardware component of the LPR2430ERA is
the CC2430 IEEE 802.15.4 compatible transceiver with
integrated 8051 microcontroller. The LPR2430ERA op-
erates in the frequency band of 2405 to 2475 MHz at a
nominal output power of 63 mW.
The LPR2430ERA includes a low noise preamplifier in
the receiver path and a power amplifier in the transmit-
ter path, greatly increasing the operating range of the
CC2430. Two crystals are provided to operate the
CC2430, a 32 MHz crystal for normal operation and a
32.768 kHz crystal for precision sleep mode operation.
The LPR2430ERA provides a variety of application
hardware interfaces including a UART interface, three
11-bit ADC inputs, two PWM (DAC) outputs, and six
general purpose digital I/O ports.
LPR2430ERA Firmware
The main firmware components in the LPR2430ERA
include the 802.15.4 Media Access Control (MAC) layer
and the CNL V2.0 Networking Layer. CNL V2.0 sup-
ports up to 63 remotes. Network topologies include
point-to-point, point-to-multipoint and peer-to-peer. CNL
employs one-hop relay forwarding to mitigate network
transmission problems such as multipath fading. CNL
includes provisions for low-power sleep mode operation
with periodic wakeup and report. The CNL Application
Programming Interface (API) provides an easy-to-use,
flexible set of application commands and functions.
The API includes support for send/receive serial data,
read/write GPIO, read ADC inputs, write PWM outputs
and module configuration services. In addition, CNL
supports analog and digital I/O binding, which maps an
ADC measurement and the states of two digital inputs
on one LPR2430ERA to a PWM output and two digital
outputs on another LPR2430ERA. See the
LPR2430
Series Integration Guide
for complete details of the
CNL API.
www.RFM.com E-mail: info@rfm.com
©2009 by RF Monolithics, Inc.
Page 3 of 5
LPR2430ERA - 06/19/09
LPR2430ERA I/O Pad Descriptions
Pin
1
2
3
4
5
6
7
Name
GND
ACTIVITY
LINK
GPIO0
(ADC_REF)
RADIO_TXD
RADIO_RXD
GPIO4
(/HOST_CTS )
GPIO5
(/HOST_RTS)
PWM0
GPIO2
(PWM1)
GPIO1
GPIO3
(RS485_EN)
PWM1
(GPIO2)
VCC
GND
GND
/RESET
ADC0
ADC1
RSVD
RSVD
RSVD
RSVD
ADC2
ADC_VDD
NC
NC
GND
NC
GND
-
I/O
-
O
O
I/O
O
I
I/O
Description
Power supply and signal ground. Connect to the host circuit board ground.
RF activity indicator. Output pulses high when a packet is sent or received.
Link indicator. Output is high when the radio has successfully joined a network.
Configurable digital I/O port 0. When configured as an output, the power-on state is also configurable. This pin can also
be configured as a reference voltage input for the ADCs, 0 to 3.3 V, 1.25 V typical.
Serial data output (UART) from the radio to the host.
Serial data input (UART) from the host to the radio.
Configurable digital I/O port 4. When configured as an output, the power-on state is also configurable. Also configurable
as UART flow control output. The LPR2430 sets this line low to indicate it is ready to accept data from the host on the
RADIO_RXD input. When the LPR2430 sets this line high, the host must stop sending data. The default state is GPIO4.
Configurable digital I/O port 5. When configured as an output, the power-on state is also configurable. Also configurable
as UART flow control input. The host sets this line low to allow data to flow from the RADIO_TXD pin. When the host sets
this line high, the LPR2430 will stop sending data to the host. The default state is GPIO5
.
Pulse-width modulated output 0 with internal low-pass filter. Provides a DAC function, 0 to 3.3 V.
Configurable digital I/O port 2. When configured as an output, the power-on state is also configurable. This pin is con-
nected to the input of the low-pass filter driving Pin 13, and is also configurable as a PWM output.
Configurable digital I/O port 1. When configured as an output, the power-on state is also configurable.
Configurable digital I/O port 3. When configured as an output, this high current port can sink up to 20 mA. The power-on
output state is also configurable. Can also be configured as active low transmit enable for controlling an RS485 or other
half-duplex bus driver.
GPIO2 (Pin 10) drives this pin through a low-pass filter. Provides a DAC function when GPIO2 is configured as a PWM
output.
Power supply input, +3.3 to +5.5 Vdc.
Power supply and signal grounds. Connect to the host circuit board ground.
Power supply and signal grounds. Connect to the host circuit board ground.
Active low module hardware reset. Hold this input low when the power supply input is less than 3.3 Vdc. The module firm-
ware boots up and will accept commands about 3 seconds after this input goes high.
11-bit ADC input 0. ADC full scale reading can be referenced to the module’s +3.3 V regulated supply, the ADC’s internal
+2.5 V reference, or ADC_REF (Pin 4).
ADC input 1. Same configuration options as ADC0.
Reserved pin. Leave unconnected.
Reserved pin. Leave unconnected.
Reserved pin. Leave unconnected.
Reserved pin. Leave unconnected.
ADC input 2. Same configuration options as ADC0.
Module’s +3.3 V regulated supply, used for ratiometric ADC readings. Current drain should be less than 5 mA.
No connection.
No connection.
RF ground. Connect to the host circuit board ground plane, and to shield when using coaxial cable.
No connection.
RF ground. Connect to the host circuit board ground plane, and to shield when using coaxial cable.
8
9
10
11
12
I/O
O
I/O
I/O
I/O
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
O
I
-
-
I
I
I
-
-
-
-
I
O
-
-
-
-
www.RFM.com E-mail: info@rfm.com
©2009 by RF Monolithics, Inc.
Page 4 of 5
LPR2430ERA - 06/19/09
L P R 2 4 3 0 E R A O u tlin e a n d M o u n tin g D im e n s io n s
0 .0 4
1 5
1 .1 5
0 .0 5
1
0 .3 0
0 .0 3
A n te n n a
0 .9 8 5
T o p V ie w
1 6
3 0
0 .1 1
D im e n s io n s in in c h e s
0 .1 2
Figure 2
Reflow Profile
An example solder reflow profile for mounting the radio module on its host circuit board is shown in Figure 3.
Figure 3
Note: Specifications subject to change without notice.
Part # M-2430-0005, Rev A
www.RFM.com E-mail: info@rfm.com
©2009 by RF Monolithics, Inc.
Page 5 of 5
LPR2430ERA - 06/19/09
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