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SMSC LAN9500A
USER MANUAL
Revision 1.0 (02-02-10)
LAN9500A Evaluation Board User Manual
1 Introduction
The LAN9500A is a high performance, small form factor solution for USB to 10/100 Ethernet port
bridging. With applications ranging from embedded systems, set-top boxes, and PVR’s, to USB port
replicators, USB to Ethernet adapters, PC docking stations, and test instrumentation, the LAN9500A
is targeted as a high performance, low cost USB/Ethernet connectivity solution.
The LAN9500A contains an integrated 10/100 Ethernet PHY, USB PHY, Hi-Speed USB 2.0 device
controller, 10/100 Ethernet MAC, TAP controller, EEPROM controller, and a FIFO controller with a total
of 30 KB of internal packet buffering. The LAN9500A complies with the IEEE 802.3 (full/half-duplex
10BASE-T and 100BASE-TX) Ethernet protocol and USB 2.0 specification, enabling compatibility with
industry standard Fast Ethernet and USB 2.0 applications.
The EVB-LAN9500A-MII is an Evaluation Board (EVB) that utilizes the LAN9500A to provide a fully
functional, USB to Ethernet interface. The EVB-LAN9500A-MII provides fully integrated Ethernet and
USB ports via the onboard RJ45 and USB Type B connectors. The EVB-LAN9500A-MII can be
configured for bus- or self-powered operation and supports internal and external PHY modes. An
external PHY may be connected via the onboard 40-pin female MII connector. The onboard 256x8
EEPROM is used to load the EVB-LAN9500A-MII’s USB configuration parameters and MAC address.
LAN9500A software drivers are available for Windows XP, Windows Vista, Mac OS X, Linux, and
Windows CE. Additional manufacturing and diagnostic tools are available for debugging and external
EEPROM configuration. For complete details, refer to the “LAN9500A Software User Manual”.
A simplified block diagram of the EVB-LAN9500A-MII can be seen in
Figure 1.1.
External PHY
JTAG Header
2 x 20
40-Pin MII Connector
(Female)
256 x 8
µWire
EEPROM
SMSC
LAN9500A
USB
USB Type B
Connector
10/100
Ethernet
Magnetics
& RJ45
Ethernet
1 x 10
GPIO Header
EVB-LAN9500A-MII
Figure 1.1 EVB-LAN9500A-MII Block Diagram
Revision 1.0 (02-02-10)
USER MANUAL
2
SMSC LAN9500A
LAN9500A Evaluation Board User Manual
1.1
References
Concepts and material available in the following documents may be helpful when using the EVB-
LAN9500A-MII.
Table 1.1 References
DOCUMENT
LOCATION
http://www.smsc.com/lan9500a
http://www.smsc.com/lan9500a
http://www.smsc.com/lan9500a
http://www.smsc.com/lan9500a
SMSC LAN9500A Datasheet
AN8-13 Suggested Magnetics
SMSC EVB-LAN9500A-MII Evaluation Board Schematic
SMSC LAN9500A Software User Manual
2 Board Details
This section includes the following EVB-LAN9500A-MII board details:
Configuration
Mechanicals
2.1
Configuration
The following sub-sections describe the various board features including jumpers, LEDs, test points,
and system connections. A top view of the EVB-LAN9500A-MII is shown in
Figure 2.1.
SMSC LAN9500A
USER MANUAL
3
Revision 1.0 (02-02-10)
LAN9500A Evaluation Board User Manual
GPIO/Strap
Header
Reset
Switch
JP2
J5
JTAG
Header
JP7
USB Type B
Connector
Female MII
Connector
MII
Testpoints
JP3 –
JP6
LAN9500A
JP1
+5V Power
Input
Ethernet Port
(integrated LEDs)
Figure 2.1 EVB-LAN9500A-MII Top View
Note:
The EVB-LAN9500A-MII includes a 2A fuse (F1) to protect from overcurrent conditions. If this
fuse becomes damaged, it can be replaced with a 2A Littlefuse-154002.
2.1.1
Jumpers
The following table details the jumper definitions and default settings for the EVB-LAN9500A-MII.
Jumper settings may be changed as needed. However, any deviation from the default settings should
be approached with care and knowledge of the schematics and datasheet. An incorrect jumper setting
may disable the board.
Note:
A dashed line in the
Settings
column indicates an installed jumper. All jumper settings are
shown in their default state (self-powered, internal Ethernet PHY operation).
Table 2.1 Jumpers
JUMPER
DESCRIPTION
SETTINGS
IN:
Connects shared JTAG signals to
JTAG header J2
OUT:
Disconnects shared JTAG signals
from JTAG header J2
Selects external Ethernet PHY
Selects internal LAN9500A Ethernet PHY
JP2
JTAG Header Connect
1
1
2
2
JP3
Ethernet PHY Select
2---3
Revision 1.0 (02-02-10)
USER MANUAL
4
SMSC LAN9500A
LAN9500A Evaluation Board User Manual
Table 2.1 Jumpers (continued)
JUMPER
DESCRIPTION
SETTINGS
IN:
Onboard +5V supplied to MII
connector pins 1, 20, 21, and 40
OUT:
Onboard +5V not supplied to MII
connector pins 1, 20, 21, and 40
Populate when bus-powered. Connects
VCC_USB from the upstream host USB
connector to the onboard +3.3V voltage
regulator input.
Populate when self-powered. Connects
+5V from the external power supply to
the onboard +3.3V voltage regulator
input.
IN:
Connects output of onboard +3.3V
regulator to the +3.3V power plane
OUT:
Disconnects output of onboard
+3.3V regulator from the +3.3V power
plane
Populate when bus-powered. Connects
+3.3V voltage regulator output to
VBUS_DET.
Populate when self-powered. Connects
VCC_USB from the upstream host USB
connector to VBUS_DET through a
voltage divider and transient filter.
JP4
MII Connector +5V Select
1
2
1
JP5
+5V Power Supply Select
(Note
2.1)
2
2---3
JP6
Onboard +3.3V Regulator
Output Connect
(Note
2.2)
1---2
1
JP7
VBUS_DET Input Select
(Note
2.1)
2
2---3
Note 2.1
Note 2.2
JP5 and JP7 must be populated indentically.
This jumper should only be removed if the customer supplies +3.3V from an external
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