COM20020ILJP datasheet, PDF - EEWORLD Datasheet

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COM20020ILJP: DescriptionNetwork controller and processor IC arcnet contrllr; Categorysemiconductor Other integrated circuit (IC); File Size409KB，72 Pages; ManufacturerAll Sensors

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COM20020ILJP Overview

Network controller and processor IC arcnet contrllr

COM20020ILJP Parametric

Parameter Name	Attribute value
Maker	All Sensors
Product Category	Network Controllers and Processor ICs
RoHS	no
product	Controller Area Network (CAN)
Transceiver quantity	1
data rate	5 Mbps
Supply voltage (maximum)	5.5 V
Supply voltage (minimum)	4.5 V
Supply current (maximum)	40 mA (Typ)
Maximum operating temperature	+ 85 C
Minimum operating temperature	- 40 C
Package/box	PLCC-28
Installation style	SMD/SMT

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COM20020I Rev D

5Mbps ARCNET (ANSI

878.1) Controller with

2K x 8 On-Chip RAM

Datasheet

Product Features

New Features for Rev. D

−

Data Rates up to 5 Mbps

−

Programmable Reconfiguration Times

Eight, 256 Byte Pages Allow Four Pages TX

and RX Plus Scratch-Pad Memory

Next ID Readable

Internal Clock Scaler and Clock Multiplier for

Adjusting Network Speed

Operating Temperature Range of -40

C to

+85

Self-Reconfiguration Protocol

Supports up to 255 Nodes

Supports Various Network Topologies (Star,

Tree, Bus...)

CMOS, Single +5V Supply

Duplicate Node ID Detection

Powerful Diagnostics

Receive All Packets Mode

Flexible Media Interface:

−

Traditional Hybrid Interface For Long

Distances up to Four Miles at 2.5 Mbps

−

RS485 Differential Driver Interface For Low

Cost, Low Power, High Reliability

28 Pin PLCC and 48 Pin TQFP Packages;

Lead-free RoHS Compliant Packages also

Available

Ideal for Industrial/Factory/Building

Automation and Transportation Applications

Deterministic, (ANSI 878.1), Token Passing

ARCNET Protocol

Minimal Microcontroller and Media Interface

Logic Required

Flexible Interface For Use With All

Microcontrollers or Microprocessors

Automatically Detects Type of

Microcontroller Interface

2Kx8 On-Chip Dual Port RAM

Command Chaining for Packet Queuing

Sequential Access to Internal RAM

Software Programmable Node ID

ORDERING INFORMATION

Order Numbers:

COM20020ILJP for 28 pin PLCC package

COM20020I-DZD for 28 pin PLCC lead-free RoHS compliant package

COM20020I-HD for 48 pin TQFP package

COM20020I-HT for 48 pin TQFP lead-free RoHS compliant package

SMSC COM20020I Rev D

Page 1

Revision 12-05-06

DATASHEET

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Datasheet

80 Arkay Drive

Hauppauge, NY 11788

(631) 435-6000

FAX (631) 273-3123

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete

information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no

responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without

notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does

not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC

or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard

Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors

known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.

SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause

or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further

testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale

Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems

Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES

OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND

ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY

DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR

REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC

OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO

HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH

DAMAGES.

Revision 12-05-06

Page 2

SMSC COM20020I Rev D

DATASHEET

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Datasheet

Table of Contents

Chapter 1

Chapter 2

Chapter 3

Chapter 4

General Description................................................................................................................ 6

Pin Configurations .................................................................................................................. 7

Description of Pin Functions .................................................................................................. 9

Protocol Description ............................................................................................................. 12

4.1

Network Protocol ........................................................................................................................................12

4.2

Data Rates .................................................................................................................................................12

4.2.1

Selecting Clock Frequencies Above 2.5 Mbps....................................................................................12

4.3

Network Reconfiguration ............................................................................................................................13

4.4

Broadcast Messages..................................................................................................................................14

4.5

Extended Timeout Function .......................................................................................................................14

4.5.1

Response Time ...................................................................................................................................14

4.5.2

Idle Time .............................................................................................................................................14

4.5.3

Reconfiguration Time ..........................................................................................................................14

4.6

Line Protocol ..............................................................................................................................................14

4.6.1

Invitations To Transmit........................................................................................................................15

4.6.2

Free Buffer Enquiries ..........................................................................................................................15

4.6.3

Data Packets.......................................................................................................................................15

4.6.4

Acknowledgements .............................................................................................................................16

4.6.5

Negative Acknowledgements ..............................................................................................................16

Chapter 5

System Description .............................................................................................................. 17

5.1

Microcontroller Interface.............................................................................................................................17

5.1.1

High Speed CPU Bus Timing Support ................................................................................................20

5.2

Transmission Media Interface ....................................................................................................................21

5.2.1

Traditional Hybrid Interface .................................................................................................................21

5.2.2

Backplane Configuration .....................................................................................................................21

5.2.3

Differential Driver Configuration ..........................................................................................................23

5.2.4

Programmable TXEN Polarity .............................................................................................................23

Chapter 6

Functional Description.......................................................................................................... 26

6.1

Microsequencer..........................................................................................................................................26

6.2

Internal Registers .......................................................................................................................................27

6.2.1

Interrupt Mask Register (IMR) .............................................................................................................27

6.2.2

Data Register ......................................................................................................................................28

6.2.3

Tentative ID Register ..........................................................................................................................28

6.2.4

Node ID Register.................................................................................................................................28

6.2.5

Next ID Register..................................................................................................................................28

6.2.6

Status Register....................................................................................................................................29

6.2.7

Diagnostic Status Register ..................................................................................................................29

6.2.8

Command Register .............................................................................................................................29

6.2.9

Address Pointer Registers ..................................................................................................................29

6.2.10

Configuration Register.....................................................................................................................29

6.2.11

Sub-Address Register .....................................................................................................................29

6.2.12

Setup 1 Register..............................................................................................................................30

6.2.13

Setup 2 Register..............................................................................................................................30

6.3

Internal RAM ..............................................................................................................................................40

6.3.1

Sequential Access Memory.................................................................................................................40

6.3.2

Access Speed .....................................................................................................................................40

6.4

Software Interface ......................................................................................................................................40

6.4.1

Selecting RAM Page Size ...................................................................................................................41

6.4.2

Transmit Sequence .............................................................................................................................42

6.4.3

Receive Sequence ..............................................................................................................................44

6.5

Command Chaining....................................................................................................................................45

6.5.1

Transmit Command Chaining .............................................................................................................45

6.5.2

Receive Command Chaining ..............................................................................................................46

6.6

Reset Details..............................................................................................................................................47

6.6.1

Internal Reset Logic ............................................................................................................................47

6.7

Initialization Sequence ...............................................................................................................................47

6.7.1

Bus Determination...............................................................................................................................47

SMSC COM20020I Rev D

Page 3

Revision 12-05-06

DATASHEET

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Datasheet

6.8

Improved Diagnostics.................................................................................................................................48

6.8.1

Normal Results:...................................................................................................................................48

6.8.2

Abnormal Results:...............................................................................................................................48

6.9

Oscillator ....................................................................................................................................................49

Chapter 7

7.1

7.2

Operational Description........................................................................................................ 50

Maximum Guaranteed Ratings* .................................................................................................................50

DC Electrical Characteristics......................................................................................................................50

Chapter 8

Timing Diagrams .................................................................................................................. 53

Chapter 9

Package Outlines ................................................................................................................. 66

Appendix A.................................................................................................................................................. 68

Appendix B - Example of Interface Circuit Diagram to ISA Bus ............................................................. 71

Appendix C - Software Identification of the COM20020 Rev B, Rev C and Rev D ................................ 72

List of Figures

Figure 2.1 - Pin Configuration - COM20020I 28-Pin PLCC ............................................................................................7

Figure 2.2 - Pin Configuration - COM20020I 48-Pin TQFP ............................................................................................8

Figure 3.1 - COM20020ID Operation ...........................................................................................................................11

Figure 5.1 – Multiplexed, 8051-Like Bus Interface with RS-485 Interface....................................................................18

Figure 5.2 – Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface ............................................................19

Figure 5.3 – High Speed CPU Bus Timing – Intel CPU Mode......................................................................................20

Figure 5.4 - COM20020ID Network Using RS-485 Differential Transceivers ...............................................................22

Figure 5.5 – Dipulse Waveform for Data of 1-1-0.........................................................................................................22

Figure 5.6 - Internal Block Diagram..............................................................................................................................24

Figure 6.1 - Sequential Access Operation.....................................................................................................................39

Figure 6.2 - RAM Buffer Packet Configuration .............................................................................................................42

Figure 6.3 – Command Chaining Status Register Queue..............................................................................................44

Figure 8.1 – Multiplexed Bus, 68XX-Like Control Signals; Read Cycle........................................................................53

Figure 8.2 – Multiplexed Bus, 80XX-Like Control Signals; Read Cycle........................................................................54

Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals; Write Cycle.........................................................................55

Figure 8.4 - Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.........................................................................56

Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................57

Figure 8.6 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................58

Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................59

Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................60

Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.................................................................61

Figure 8.10 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle ...............................................................62

Figure 8.11 - Normal Mode Transmit or Receive Timing..............................................................................................63

Figure 8.12 - Backplane Mode Transmit or Receive Timing ........................................................................................64

Figure 8.13 - TTL Input Timing on XTAL1 Pin..............................................................................................................65

Figure 8.14 - Reset and Interrupt Timing .....................................................................................................................65

Figure 9.1 - 28 Pin PLCC Package Dimensions...........................................................................................................66

Figure 9.2 - 48 Pin TQFP Package Outline..................................................................................................................67

Figure 0.1 - Effect of the EF Bit on the TA/RI Bit..........................................................................................................70

List of Tables

Table 5.1 - Typical Media.............................................................................................................................................24

Table 6.1 - Read Register Summary............................................................................................................................26

Table 6.2 - Write Register Summary ............................................................................................................................27

Table 6.3 - Status Register ...........................................................................................................................................31

Table 6.4 - Diagnostic Status Register..........................................................................................................................32

Table 6.5 - Command Register.....................................................................................................................................33

Table 6.6 - Address Pointer High Register ....................................................................................................................34

Table 6.7 - Address Pointer Low Register.....................................................................................................................34

Table 6.8 - Sub Address Register .................................................................................................................................34

Table 6.9 - Configuration Register ................................................................................................................................35

Revision 12-05-06

Page 4

SMSC COM20020I Rev D

DATASHEET

COM20020ILJP Related Products

	COM20020ILJP	COM20020I-DZD	COM20020I3V-DZD-TR	COM20020I3V-DZD
Description	Network controller and processor IC arcnet contrllr	Network controller and processor IC arcnet controller	Network controller and processor IC 5mbps arcnet ctrl 2K x 8 ON-chip ram	Network controller and processor IC arcnet controller
Maker	All Sensors	All Sensors	All Sensors	All Sensors
Product Category	Network Controllers and Processor ICs	Network Controllers and Processor ICs	Network Controllers and Processor ICs	Network Controllers and Processor ICs
RoHS	no	yes	yes	yes
Package/box	PLCC-28	PLCC-28	PLCC-28	PLCC-28
Installation style	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT
product	Controller Area Network (CAN)	Controller Area Network (CAN)	-	Controller Area Network (CAN)
Transceiver quantity	1	1	-	1
data rate	5 Mbps	5 Mbps	-	5 Mbps
Supply voltage (maximum)	5.5 V	5.5 V	-	3.465 V
Supply voltage (minimum)	4.5 V	4.5 V	-	3.135 V
Supply current (maximum)	40 mA (Typ)	40 mA (Typ)	-	35 mA (Typ)
Maximum operating temperature	+ 85 C	+ 85 C	-	+ 85 C
Minimum operating temperature	- 40 C	- 40 C	-	- 40 C
Encapsulation	-	Bulk	Tube	Bulk

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