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Revision 12-05-06
Page 2
SMSC COM20020I Rev D
DATASHEET
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Table of Contents
Chapter 1
Chapter 2
Chapter 3
Chapter 4
General Description................................................................................................................ 6
Data Rates .................................................................................................................................................12
Extended Timeout Function .......................................................................................................................14
4.5.1
Response Time ...................................................................................................................................14
4.5.2
Idle Time .............................................................................................................................................14
4.5.3
Reconfiguration Time ..........................................................................................................................14
4.6
Line Protocol ..............................................................................................................................................14
4.6.1
Invitations To Transmit........................................................................................................................15
Figure 5.1 – Multiplexed, 8051-Like Bus Interface with RS-485 Interface....................................................................18
Figure 5.2 – Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface ............................................................19
Figure 5.3 – High Speed CPU Bus Timing – Intel CPU Mode......................................................................................20
Figure 5.4 - COM20020ID Network Using RS-485 Differential Transceivers ...............................................................22
Figure 5.5 – Dipulse Waveform for Data of 1-1-0.........................................................................................................22
Figure 0.1 - Effect of the EF Bit on the TA/RI Bit..........................................................................................................70
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