CS43L42-KZR datasheet, PDF - EEWORLD Datasheet

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CS43L42-KZR: Descriptionaudio digital/analog converter IC IC low pwr str dac w/hdphn & line amp; Categorysemiconductor Other integrated circuit (IC); File Size1MB，40 Pages; ManufacturerCirrus Logic; Websitehttp://www.cirrus.com; Environmental Compliance

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CS43L42-KZR Overview

audio digital/analog converter IC IC low pwr str dac w/hdphn & line amp

CS43L42-KZR Parametric

Parameter Name	Attribute value
Maker	Cirrus Logic
Product Category	Audio digital/analog converter IC
RoHS	yes
Package/box	TSSOP-24
Installation style	SMD/SMT

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CS43L42

Low Voltage, Stereo DAC with Headphone Amp

Features

1.8 to 3.3 Volt supply

24-Bit conversion / 96 kHz sample rate

96 dB dynamic range at 3 V supply

-85 dB THD+N

Low power consumption

Digital volume control

•

96 dB attenuation, 1 dB step size

Description

The CS43L42 is a complete stereo digital-to-analog out-

put system including interpolation, 1-bit D/A conversion,

analog filtering, volume control, line level outputs, and a

headphone amplifier, in a 24-pin TSSOP package.

The CS43L42 is based on delta-sigma modulation,

where the modulator output controls the reference volt-

age input to an ultra-linear analog low-pass filter. This

architecture allows infinite adjustment of the sample rate

between 2 kHz and 100 kHz simply by changing the

master clock frequency.

The CS43L42 contains on-chip digital bass and treble

boost, peak signal limiting, and de-emphasis. The

CS43L42 operates from a +1.8 V to +3.3 V supply and

consumes only 16 mW of power with a 1.8 V supply with

the line amplifier powered-down. These features are

ideal for portable CD, MP3 and MD players and other

portable playback systems that require extremely low

power consumption.

Digital bass and treble boost

•

Selectable corner frequencies

•

Up to 12 dB boost in 1 dB increments

Peak signal limiting to prevent clipping

De-emphasis for 32 kHz, 44.1 kHz, and 48 kHz

Headphone amplifier

•

up to 25 mW

rms

power output into 16

Ω

load*

•

25 dB analog attenuation and mute

•

Zero crossing click free level transitions

ATAPI mixing functions

24-Pin TSSOP package

1 kHz sine wave at 3.3V supply

CS43L42-KZ

CS43L42-KZZ, Lead Free

CDB43L42

ORDERING INFORMATION

-10 to 70 °C

24-pin TSSOP

Evaluation Board

SCL/CCLK/DIF1 SDA/CDIN/DIF0

AD0/CS/DEM0

MUTEC

External

Mute Control

VQ_HP

VA_HP

RST

Control Port

Headphone

Amplifier

Analog

Volume

Control

Analog

Volume

Control

HP_A

Serial Port

Digital Filters

LRCK

SDATA

Line

Amplifier

SCLK/DEM1

Analog

Filter

Gain

Compensation

Digital

Volume

Control

Bass/Treble

Boost

Limiting

De-emphasis

∆Σ

DAC

∆Σ

DAC

Analog

Filter

HP_B

AOUTA

AOUTB

GND

MCLK

FILT+

REF_GND

VQ_LINE

VA_LINE

Preliminary Product Information

http://www.cirrus.com

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Cirrus Logic, Inc. 2004

Sep ‘04

DS481PP2

CS43L42

TABLE OF CONTENTS

1. CHARACTERISTICS/SPECIFICATIONS ....................................................... 5

ANALOG CHARACTERISTICS................................................................... 5

ANALOG CHARACTERISTICS................................................................... 6

ANALOG CHARACTERISTICS................................................................... 7

POWER AND THERMAL CHARACTERISTICS ......................................... 8

DIGITAL CHARACTERISTICS.................................................................... 9

ABSOLUTE MAXIMUM RATINGS .............................................................. 9

RECOMMENDED OPERATING CONDITIONS .......................................... 9

SWITCHING CHARACTERISTICS ........................................................... 10

SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE12

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE....... 13

2. TYPICAL CONNECTION DIAGRAM .......................................................... 14

3. REGISTER QUICK REFERENCE ................................................................ 15

4. REGISTER DESCRIPTION .......................................................................... 16

4.1 Power and Muting Control (address 01h) .......................................... 16

4.1.1 Auto-mute (AMUTE) ........................................................................ 16

4.1.2 Soft Ramp AND Zero Cross CONTROL (SZC) ................................ 16

4.1.3 Popguard® Transient Control (POR)............................................... 17

4.1.4 Power Down Headphone Amplifier (PDNHP)................................... 17

4.1.5 Power Down Line Amplifier (PDNLN) ............................................... 17

4.1.6 Power Down (PDN) .......................................................................... 17

4.2 Channel A Analog Headphone Attenuation Control (address 02h) (HVOLA)18

4.3 Channel B Analog Headphone Attenuation Control (address 03h) (hVOLB)18

4.4 Channel A Digital Volume Control (address 04h) (DVOLA) ............... 18

4.5 Channel B Digital Volume Control (address 05h) (DVOLB) ............... 18

4.6 Tone Control (address 06h)................................................................ 19

4.6.1 Bass Boost Level (BB)...................................................................... 19

4.6.2 Treble Boost Level (tb) ..................................................................... 19

4.7 Mode Control (address 07h) ............................................................... 20

4.7.1 Bass Boost Corner Frequency (bbcf) ............................................... 20

4.7.2 Treble Boost Corner Frequency (TBCF)........................................... 20

4.7.3 Channel A Volume = Channel B Volume (A=B) ............................... 20

4.7.4 De-Emphasis Control (DEM) ............................................................ 21

4.7.5 Digital Volume Control Bypass (VCBYP).......................................... 21

4.8 Limiter Attack Rate (address 08h) (ARATE)....................................... 21

4.9 Limiter Release Rate (address 09h) (RRATE) ............................... 22

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

C is a registered trademark of Philips Semiconductors.

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-

mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information

contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of

any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights

of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of

this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or

otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no

part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,

photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture

or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing

in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-

marks and service marks can be found at http://www.cirrus.com.

DS481PP2

CS43L42

4.10 Volume and Mixing Control (address 0Ah)....................................... 22

4.10.1 Tone Control MODE (TC)............................................................... 22

4.10.2 Tone Control Enable (TC_EN) ....................................................... 22

4.10.3 Peak Signal Limiter Enable (LIM_EN) ............................................ 23

4.10.4 ATAPI Channel Mixing and Muting (atapi) ..................................... 23

4.11 Mode Control 2 (address 0Bh) ......................................................... 24

4.11.1 Master Clock DIVIDE ENABLE (mclkdiv) ....................................... 24

4.11.2 Line Amplifier Gain Compensation (line) ........................................ 24

4.11.3 Digital Interface Format (dif) ........................................................... 24

5. PIN DESCRIPTION ....................................................................................... 26

6. APPLICATIONS ........................................................................................... 29

6.1 Grounding and Power Supply Decoupling ........................................ 29

6.2 Clock Modes ...................................................................................... 29

6.3 De-Emphasis ..................................................................................... 29

6.4 Recommended Power-up Sequence ................................................ 29

6.5 PopGuard® Transient Control ........................................................... 29

7. CONTROL PORT INTERFACE .................................................................... 30

7.1 SPI Mode ........................................................................................... 30

7.2 Two-Wire Mode ................................................................................. 30

7.3 Memory Address Pointer (MAP)

............................................... 31

7.3.1 INCR (Auto Map Increment Enable)................................................. 31

7.3.2 MAP0-3 (Memory Address Pointer) ................................................. 31

8. PARAMETER DEFINITIONS ........................................................................ 39

9. REFERENCES .............................................................................................. 39

10. PACKAGE DIMENSIONS ......................................................................... 40

LIST OF FIGURES

Figure 1. External Serial Mode Input Timing ............................................................ 11

Figure 2. Internal Serial Mode Input Timing ............................................................. 11

Figure 3. Internal Serial Clock Generation ............................................................... 11

Figure 4. Control Port Timing - Two-Wire Mode ....................................................... 12

Figure 5. Control Port Timing - SPI Mode ................................................................ 13

Figure 6. Typical Connection Diagram ..................................................................... 14

Figure 7. Control Port Timing, SPI mode .................................................................. 31

Figure 8. Control Port Timing, Two-Wire Mode ........................................................ 31

Figure 9. Base-Rate Stopband Rejection ................................................................. 32

Figure 10. Base-Rate Transition Band ..................................................................... 32

Figure 11. Base-Rate Transition Band (Detail) ......................................................... 32

Figure 12. Base-Rate Passband Ripple ................................................................... 32

Figure 13. High-Rate Stopband Rejection ................................................................ 32

Figure 14. High-Rate Transition Band ...................................................................... 32

Figure 15. High-Rate Transition Band (Detail) ......................................................... 33

Figure 16. High-Rate Passband Ripple .................................................................... 33

Figure 17. Line Output Test Load ............................................................................. 33

Figure 18. Headphone Output Test Load ................................................................. 33

Figure 19. CS43L42 Control Port Mode - Serial Audio Format 0 ............................. 34

Figure 20. CS43L42 Control Port Mode - Serial Audio Format 1 ............................. 34

Figure 21. CS43L42 Control Port Mode - Serial Audio Format 2 ............................. 34

Figure 22. CS43L42 Control Port Mode - Serial Audio Format 3 ............................. 35

Figure 23. CS43L42 Control Port Mode - Serial Audio Format 4 ............................. 35

Figure 24. CS43L42 Control Port Mode - Serial Audio Format 5 ............................. 35

Figure 25. CS43L42 Control Port Mode - Serial Audio Format 6 ............................. 36

Figure 26. CS43L42 Stand Alone Mode - Serial Audio Format 0 ............................. 36

DS481PP2

CS43L42-KZR Related Products

	CS43L42-KZR	CS43L42-KZZ	CS43L42-KZZR	CS43L42
Description	audio digital/analog converter IC IC low pwr str dac w/hdphn & line amp	IC dac W/hdpn amp LV 24tssop	audio digital/analog converter IC IC low pwr str dac w/hdphn & line amp	low voltage,stereo dac with headphone amp

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