A1415A-PQ100M datasheet, PDF - EEWORLD Datasheet

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A1415A-PQ100M: Descriptionfpga - field programmable gate array 1.5K system gates; CategoryProgrammable logic devices Programmable logic; File Size489KB，68 Pages; ManufacturerActel; Websitehttp://www.actel.com/

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A1415A-PQ100M Overview

fpga - field programmable gate array 1.5K system gates

A1415A-PQ100M Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Actel
package instruction	PLASTIC, MO-108, QFP-100
Reach Compliance Code	compliant
maximum clock frequency	110 MHz
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
Humidity sensitivity level	3
Configurable number of logic blocks	200
Equivalent number of gates	1500
Number of terminals	100
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	200 CLBS, 1500 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	225
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.4 mm
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm

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Accelerator Series FPGAs

– ACT

™

3 Family

Fe atur es

• Replaces up to twenty 32 macro-cell CPLDs

• Replaces up to one hundred 20-pin PAL

Packages

• Up to 1153 Dedicated Flip-Flops

• VQFP, TQFP, BGA, and PQFP Packages

• Nonvolatile, User Programmable

• Fully Tested Prior to Shipment

• 5.0V and 3.3V Versions

• Optimized for Logic Synthesis Methodologies

• Low-power CMOS Technology

A1415

1,500

3,750

200

104

264

100

—

100

—

108 MHz

63 MHz

110 MHz

250 MHz

7.5 ns

A1425

2,500

6,250

310

160

150

360

100

133

100, 160

—

100

—

132

108 MHz

63 MHz

110 MHz

250 MHz

7.5 ns

A1440

4,000

10,000

100

564

288

276

568

140

175

160

—

100

176

—

100 MHz

63 MHz

110 MHz

250 MHz

8.5 ns

A1460

6,000

15,000

150

848

432

416

768

168

207

—

160, 208

—

176

225

196

97 MHz

63 MHz

110 MHz

200 MHz

9.0 ns

A14100

10,000

25,000

250

100

1,377

697

680

1,153

228

257

—

208

—

313

256

93 MHz

63 MHz

105 MHz

200 MHz

9.5 ns

• Up to 10,000 Gate Array Equivalent Gates

(up to 25,000 equivalent PLD Gates)

• Highly Predictable Performance with 100% Automatic

Placement and Routing

• 7.5 ns Clock-to-Output Times

• Up to 250 MHz On-Chip Performance

• Up to 228 User-Programmable I/O Pins

• Four Fast, Low-Skew Clock Networks

• More than 500 Macro Functions

Device

Capacity

Gate Array Equivalent Gates

PLD Equivalent Gates

TTL Equivalent Packages (40 gates)

20-Pin PAL Equivalent Packages (100 gates)

Logic Modules

S-Module

C-Module

Dedicated Flip-Flops

User I/Os (maximum)

Packages

(by pin count)

CPGA

PLCC

PQFP

RQFP

VQFP

TQFP

BGA

CQFP

Performance

(maximum, worst-case commercial)

Chip-to-Chip

Accumulators (16-bit)

Loadable Counter (16-bit)

Prescaled Loadable Counters (16-bit)

Datapath, Shift Registers

Clock-to-Output (pad-to-pad)

Notes:

1. One flip-flop per S-Module, two flip-flops per I/O-Module.

2. See product plan on page 1-178 for package availability.

3. Based on A1415A-3, A1425A-3, A1440B-3, A1460B-3, and A14100B-3.

4. Clock-to-Output + Setup

S e p t e m b e r 19 9 7

1-175

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