74LVC2952A
Octal registered transceiver with 5 V tolerant inputs/outputs;
3-state
Rev. 02 — 29 June 2004
Product data sheet
1. General description
The 74LVC2952A is a high-performance, low power, low voltage, Si-gate CMOS device
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can
handle 5 V. These features allow the use of these devices as translators in a mixed 3.3 V
and 5 V environment.
The 74LVC2952A is an octal non-inverting registered transceiver. Two 8-bit back-to-back
registers store data flowing in both directions between two bidirectional buses. Data
applied to the inputs is entered and stored on the rising edge of the clock (CPAB, CPBA)
provided that the clock enable (CEAB, CEBA) input is LOW. The data is then present at
the 3-state output buffers, but is only accessible when the output enable (OEAB, OEBA)
input is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs.
2. Features
s
s
s
s
s
s
s
s
5 V tolerant inputs/outputs for interfacing with 5 V logic
Supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Flow-through pin-out architecture
Complies with JEDEC standard JESD8-B/JESD36
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C.
Philips Semiconductors
74LVC2952A
Octal registered transceiver
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns.
Symbol
t
PHL
, t
PLH
f
max
C
I
C
I/O
C
PD
[1]
Parameter
propagation delay
CPAB, CPBA to An, Bn
input capacitance
input/output capacitance
power dissipation
capacitance per latch
Conditions
C
L
= 50 pF; V
CC
= 3.3 V
Min
-
-
-
-
Typ
3.6
250
5.0
Max Unit
-
-
-
ns
MHz
pF
pF
pF
maximum clock frequency C
L
= 50 pF; V
CC
= 3.3 V
10.0 -
15.0 -
outputs enabled;
V
CC
= 3.3 V
[1] [2]
-
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
[2]
The condition is V
I
= GND to V
CC
.
4. Ordering information
Table 2:
Ordering information
Package
Temperature range Name
74LVC2952AD
74LVC2952ADB
74LVC2952APW
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SO24
SSOP24
TSSOP24
Description
plastic small outline package; 24 leads; body
width 7.5 mm
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24
leads; body width 4.4 mm
Version
SOT137-1
SOT340-1
SOT355-1
Type number
9397 750 13251
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2004
2 of 19
Philips Semiconductors
74LVC2952A
Octal registered transceiver
6.2 Pin description
Table 3:
Symbol
B7
B6
B5
B4
B3
B2
B1
B0
OEAB
CPAB
CEAB
GND
CEBA
CPBA
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Description
B data input/output
B data input/output
B data input/output
B data input/output
B data input/output
B data input/output
B data input/output
B data input/output
A to B output enable input (active LOW)
A to B clock input (LOW-to-HIGH, edge-triggered)
A to B clock enable input (active LOW)
ground (0 V)
B to A clock enable input (active LOW)
B to A clock input (LOW-to-HIGH, edge-triggered)
B to A output enable input (active LOW)
A data input/output
A data input/output
A data input/output
A data input/output
A data input/output
A data input/output
A data input/output
A data input/output
supply voltage
9397 750 13251
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2004
5 of 19
Power technology
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