VP2450
P-Channel Enhancement-Mode
Vertical DMOS FET
Features
►
►
►
►
►
►
►
Free from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C
ISS
and fast switching speeds
High input impedance and high gain
Excellent thermal stability
Integral source-to-drain diode
General Description
The Supertex VP2450 is an enhancement-mode (normally-
off) transistor that utilizes a vertical DMOS structure
and Supertex’s well-proven silicon-gate manufacturing
process. This combination produces a device with the
power handling capabilities of bipolar transistors, and the
high input impedance and positive temperature coefficient
inherent in MOS devices. Characteristic of all MOS
structures, this device is free from thermal runaway and
thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Applications
►
►
►
►
►
►
Motor controls
Converters
Amplifiers
Switches
Power supply circuits
Drivers (relays, hammers, solenoids, lamps,
memories, displays, bipolar transistors, etc.)
Ordering Information
Device
VP2450
Package Options
TO-92
VP2450N3-G
TO-243AA (SOT-89)
VP2450N8-G
BV
DSS
/BV
DGS
(V)
R
DS(ON)
(max)
(Ω)
I
D(ON)
(min)
(mA)
-500
30
-200
-G indicates package is RoHS compliant (‘Green’)
Pin Configurations
DRAIN
SOURCE
DRAIN
Absolute Maximum Ratings
Parameter
Drain-to-Source voltage
Drain-to-Gate voltage
Gate-to-Source voltage
Operating and storage temperature
Soldering temperature*
Value
BV
DSS
BV
DGS
±20V
-55
O
C to +150
O
C
300
O
C
GATE
GATE
SOURCE
DRAIN
TO-92 (N3)
TO-243AA (SOT-89) (N8)
Product Marking
S iV P
2 45 0
YYWW
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
*
Distance of 1.6mm from case for 10 seconds.
Package may or may not include the following marks: Si or
TO-92 (N3)
VP4EW
W = Code for week sealed
= “Green” Packaging
Packages may or may not include the following marks: Si or
TO-243AA (SOT-89) (N8)
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
VP2450
Thermal Characteristics
Package
TO-92
TO-243AA (SOT-89)
†
‡
(continuous)
(mA)
I
D
†
(pulsed)
(mA)
I
D
Power Dissipation
@T
C
= 25
O
C
(W)
O
( C/W)
θ
jc
( C/W)
O
θ
ja
(mA)
I
DR
†
(mA)
I
DRM
-100
-160
-300
-800
1.0
1.6
‡
125
15
170
78
-100
-160
-300
-800
I
D
(continuous) is limited by max rated T
j
.
Mounted on FR5 board, 25mm x 25mm x 1.57mm.
= 25
O
C unless otherwise specified)
Electrical Characteristics
(T
Sym
BV
DSS
V
GS(th)
ΔV
GS(th)
I
GSS
I
DSS
I
D(ON)
R
DS(ON)
ΔR
DS(ON)
G
FS
C
ISS
C
OSS
C
RSS
t
d(ON)
t
r
t
d(OFF)
t
f
V
SD
t
rr
Parameter
Gate threshold voltage
A
Min
-500
-1.5
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
320
-
-
-
-
-
-
-
-
300
Max
-
-3.5
-4.8
-100
-10
-1.0
-
-
35
30
0.75
-
190
75
20
10
25
45
25
-1.8
-
Units
V
V
nA
µA
mA
mA
Ω
%/
O
C
Conditions
V
GS
= 0V, I
D
= -250µA
V
GS
= V
DS
, I
D
= -1.0mA
V
GS
= ± 20V, V
DS
= 0V
V
GS
= 0V, V
DS
= Max Rating
V
DS
= 0.8 Max Rating,
V
GS
= 0V, T
A
= 125°C
V
GS
= -4.5V, V
DS
= -15V
V
GS
= -10V, V
DS
= -15V
V
GS
= -4.5V, I
D
= -50mA
V
GS
= -10V, I
D
= -100mA
V
GS
= -10V, I
D
= -100mA
V
GS
= 0V,
V
DS
= -25V,
f = 1.0MHz
V
DD
= -25V,
I
D
= -200mA,
R
GEN
= 25Ω
V
GS
= 0V, I
SD
= -100mA
V
GS
= 0V, I
SD
= -100mA
Drain-to-source breakdown voltage
Change in V
GS(th)
with temperature
Gate body leakage
Zero gate voltage drain current
mV/
O
C V
GS
= V
DS
, I
D
= -1.0mA
-
-75
-200
-
-
-
150
-
-
-
-
-
-
-
-
-
On-state drain current
Static drain-to-source on-state resistance
Change in R
DS(ON)
with temperature
Forward transductance
Input capacitance
Common source output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Diode forward voltage drop
Reverse recovery time
mmho V
DS
= -15V, I
D
= -100mA
pF
ns
V
ns
Notes:
1. All D.C. parameters 100% tested at 25
O
C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
0V
10%
90%
t
(OFF)
INPUT
-10V
PULSE
GENERATOR
t
(ON)
R
GEN
t
F
INPUT
t
d(ON)
0V
t
r
t
d(OFF)
D.U.T.
Output
R
L
10%
OUTPUT
V
DD
90%
10%
90%
V
DD
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
2
VP2450
3-Lead TO-92 Package Outline (N3)
D
A
Seating Plane
1
2
3
L
e1
e
b
c
Front View
Side View
E1
E
1
2
3
Bottom View
Symbol
Dimensions
(inches)
MIN
NOM
MAX
A
.170
-
.210
b
.014
†
-
.022
†
c
.014
†
-
.022
†
D
.175
-
.205
E
.125
-
.165
E1
.080
-
.105
e
.095
-
.105
e1
.045
-
.055
L
.500
-
.610*
JEDEC Registration TO-92.
* This dimension is not specified in the original JEDEC drawing. The value listed is for reference only.
† This dimension is a non-JEDEC dimension.
Drawings not to scale.
Supertex Doc.#:
DSPD-3TO92N3, Version D080408.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
5
Microcontroller MCU
京公网安备 11010802033920号
EEWORLD
