UPD46365092BF1-E33Y-EQ1 datasheet, PDF

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UPD46365092BF1-E33Y-EQ1: DescriptionQDR SRAM; Categorystorage storage; File Size610KB，36 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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UPD46365092BF1-E33Y-EQ1 Overview

QDR SRAM

UPD46365092BF1-E33Y-EQ1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	1277419876
package instruction	BGA-165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Samacsys Description	QDRII/DDRII/ QDRII+/DDRII+ SRAM
Samacsys Manufacturer	Renesas Electronics
Samacsys Modified On	2022-04-28 13:17:55
Maximum access time	0.45 ns
Maximum clock frequency (fCLK)	300 MHz
I/O type	SEPARATE
JESD-30 code	R-PBGA-B165
length	15 mm
memory density	37748736 bit
Memory IC Type	QDR SRAM
memory width	9
Number of functions	1
Number of terminals	165
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4MX9
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.46 mm
Maximum standby current	0.43 A
Minimum standby current	1.7 V
Maximum slew rate	0.7 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

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Datasheet

PD46365092B

PD46365182B

PD46365362B

36M-BIT QDR

II SRAM

2-WORD BURST OPERATION

Description

The

PD46365092B is a 4,194,304-word by 9-bit, the

PD46365182B is a 2,097,152-word by 18-bit and the

PD46365362B is a 1,048,576-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS

technology using full CMOS six-transistor memory cell.

The

PD46365092B,

PD46365182B and

PD46365362B integrate unique synchronous peripheral circuitry and a

burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and

K#.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA.

R10DS0089EJ0400

Rev.4.00

Nov 09, 2012

Features

•

1.8 ± 0.1 V power supply

•

165-pin PLASTIC BGA (13 x 15)

•

HSTL interface

•

PLL circuitry for wide output data valid window and future frequency scaling

•

Separate independent read and write data ports with concurrent transactions

•

100% bus utilization DDR READ and WRITE operation

•

Two-tick burst for low DDR transaction size

•

Two input clocks (K and K#) for precise DDR timing at clock rising edges only

•

Two output clocks (C and C#) for precise flight time and clock skew matching-clock

and data delivered together to receiving device

•

Internally self-timed write control

•

Clock-stop capability. Normal operation is restored in 20

s after clock is resumed.

•

User programmable impedance output (35 to 70

Ω)

•

Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz).

•

Simple control logic for easy depth expansion

•

JTAG 1149.1 compatible test access port

R10DS0089EJ0400 Rev.4.00

Nov 09, 2012

Page 1 of 35

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