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74AUP2G00GT-G

Description
Gate (AND/NAND/OR/NOR) 1.8V dual 2-input nand gate
Categorylogic    logic   
File Size172KB,21 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
Download Datasheet Parametric View All

74AUP2G00GT-G Overview

Gate (AND/NAND/OR/NOR) 1.8V dual 2-input nand gate

74AUP2G00GT-G Parametric

Parameter NameAttribute value
Source Url Status Check Date2013-06-14 00:00:00
Is it lead-free?Contains lead
Is it Rohs certified?conform to
MakerNXP
Reach Compliance Codeunknow
Base Number Matches1
74AUP2G00
Low-power dual 2-input NAND gate
Rev. 5 — 21 October 2010
Product data sheet
1. General description
The 74AUP2G00 provides dual 2-input NAND function.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1 000 V
Low static power consumption; I
CC
= 0.9
μA
(maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
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