DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
2
R-DNL
R
WB
, V
A
= No Connect
R-INL
R
WB
, V
A
= No Connect
Resistor Nonlinearity Error
2
3
∆R
AB
T
A
= +25°C
Nominal Resistor Tolerance
V
AB
= V
DD
, Wiper = No Connect
Resistance Temperature Coefficient
∆R
AB
/∆T
CH1 to 2, 3, 4, or 5, 6; V
AB
= V
DD
Nominal Resistance Match
∆R/R
AB
Wiper Resistance
R
W
I
W
= 1 V/R, V
DD
= +5 V
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution
N
4
DNL
Differential Nonlinearity
4
INL
Integral Nonlinearity
Code = 40
H
Voltage Divider Temperature Coefficient
∆V
W
/∆T
Code = 7F
H
Full-Scale Error
V
WFSE
Zero-Scale Error
V
WZSE
Code = 00
H
RESISTOR TERMINALS
Voltage Range
5
Capacitance
6
Ax, Bx
Capacitance
6
Wx
Shutdown Current
7
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance
6
POWER SUPPLIES
Power Single Supply Range
Power Dual Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
8
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
6, 9
Bandwidth –3 dB
V
A,
V
B,
V
W
C
A,
C
B
C
W
I
A_SD
I
CM
V
IH
V
IL
V
OH
V
OL
I
IL
C
IL
V
DD
Range
V
DD/SS
Range
I
DD
I
SS
P
DISS
PSS
BW_10K
BW_50K
BW_100K
THD
W
t
S
e
N_WB
±
1/4
±
1/2
15
–1
+1
+1
+2
0
+2
V
DD
f = 1 MHz, Measured to GND, Code = 40
H
f = 1 MHz, Measured to GND, Code = 40
H
V
A
= V
B
= V
W
= 0, V
DD
= +2.7 V, V
SS
= –2.5 V
V
DD
= +5 V/+3 V
V
DD
= +5 V/+3 V
R
PULL–UP
= 1 kΩ to +5 V
I
OL
= 1.6 mA, V
LOGIC
= +5 V
V
IN
= 0 V or +5 V
2.4/2.1
45
60
0.01
1
5
0.8/0.6
4.9
0.4
±
1
5
V
SS
= 0 V
V
IH
= +5 V or V
IL
= 0 V
V
SS
= –2.5 V, V
DD
= +2.7 V
V
IH
= +5 V or V
IL
= 0 V
∆V
DD
= +5 V
±
10%
R
AB
= 10 kΩ
R
AB
= 50 kΩ
R
AB
= 100 kΩ
V
A
= 1.414 V rms, V
B
= 0 V dc, f = 1 kHz
V
A
= 5 V, V
B
= 0 V,
±
1 LSB Error Band
R
WB
= 5 kΩ, f = 1 kHz,
PR
= 0
2.7
±
2.3
12
12
0.0002
721
137
69
0.004
2/9/18
9
20
5
5
1
15
40
90
0
0
10
5.5
±
2.7
60
60
0.3
0.005
Total Harmonic Distortion
V
W
Settling Time (10K/50K/100K)
Resistor Noise Voltage
INTERFACE TIMING CHARACTERISTICS Applies to All Parts
6, 10
Input Clock Pulsewidth
t
CH
, t
CL
Clock Level High or Low
Data Setup Time
t
DS
Data Hold Time
t
DH
11
t
PD
R
L
= 2 kΩ, C
L
< 20 pF
CLK to SDO Propagation Delay
CS
Setup Time
t
CSS
CS
High Pulsewidth
t
CSW
Reset Pulsewidth
t
RS
CLK Fall to
CS
Fall Setup
t
CSH0
CLK Fall to
CS
Rise Hold Time
t
CSH1
CS
Rise to Clock Rise Setup
t
CS1
NOTES
1
2
150
Typicals represent average readings at +25°C and V
DD
= +5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 23 test circuit. I
W
= V
DD
/R
for both V
DD
= +3 V or V
DD
= +5 V.
3
V
AB
= V
DD
, Wiper (V
W
) = No connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of
±1
LSB maximum are guaranteed monotonic operating conditions. See Figure 22 test circuit.
–2–
REV. 0
AD5204/AD5206
Resistor Terminals A, B, W, have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
7
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8
P
DISS
is calculated from (I
DD
×
V
DD
). CMOS logic level inputs result in minimum power dissipation.
9
All dynamic characteristics use V
DD
= +5 V.
10
See timing diagrams for location of measured values. All input control voltages are specified with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V. Switching characteristics are measured using both V
京公网安备 11010802033920号
EEWORLD
