a
FEATURES
128 Position
Potentiometer Replacement
10 k , 50 k , 100 k
Very Low Power: 40 A Max
Increment/Decrement Count Control
APPLICATIONS
Mechanical Potentiometer Replacement
Remote Incremental Adjustment Applications
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
GENERAL DESCRIPTION
CLK
CS
Increment/Decrement
Digital Potentiometer
AD5220
FUNCTIONAL BLOCK DIAGRAM
V
DD
EN
UP/
7
DOWN
CNTR
RS
POR
40
H
D
E
C
O
D
E
A
W
B
GND
U/D
AD5220
+5V
UP/DOWN
CS
U/D
CLK
The AD5220 provides a single channel, 128-position digitally
controlled variable resistor (VR) device. This device performs
the same electronic adjustment function as a potentiometer or
variable resistor. These products were optimized for instrument
and test equipment push-button applications. A choice between
bandwidth or power dissipation are available as a result of the
wide selection of end-to-end terminal resistance values.
The AD5220 contains a fixed resistor with a wiper contact that
taps the fixed resistor value at a point determined by a digitally
controlled UP/DOWN counter. The resistance between the
wiper and either end point of the fixed resistor provides a con-
stant resistance step size that is equal to the end-to-end resis-
tance divided by the number of positions (e.g., R
STEP
= 10 kΩ/
128 = 78
Ω).
The variable resistor offers a true adjustable value
of resistance, between the A terminal and the wiper, or the B
terminal and the wiper. The fixed A-to-B terminal resistance of
10 kΩ, 50 kΩ, or 100 kΩ has a nominal temperature coefficient
of 800 ppm/°C.
The chip select
CS,
count CLK and U/D direction control
inputs set the variable resistor position. These inputs that con-
trol the internal UP/DOWN counter can be easily generated
with mechanical or push button switches (or other contact closure
devices). External debounce circuitry is required for the nega-
tive-edge sensitive CLK pin. This simple digital interface elimi-
nates the need for microcontrollers in front panel interface designs.
The AD5220 is available in both surface mount (SO-8) and the
8-lead plastic DIP package. For ultracompact solutions selected
models are available in the thin
µSOIC
package. All parts are
guaranteed to operate over the extended industrial temperature
range of –40°C to +85°C. For 3-wire, SPI compatible inter-
face applications, see the AD7376/AD8400/AD8402/AD8403
products.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
INCREMENT
AD5220
Figure 1. Typical Push-Button Control Application
50mV/DIV
UPCOUNT DETAIL
V
DD
= 5.5V
V
A
= 5.5V
V
B
= 0V
f = 100kHz
V
WB
5V/DIV
CLK
Figure 2a. Stair-Step Increment Output
V
DD
= 5.5V
V
A
= 5.5V
V
B
= 0V
f = 60kHz
COUNT
00
H
v
3F
H
v
00
H
V
WR
f
CLK
= 60kHz
Figure 2b. Full-Scale Up/Down Count
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
ELECTRICAL CHARACTERISTICS
Parameter
AD5220–SPECIFICATIONS
= +3 V
(V
DD
10% or +5 V
otherwise noted)
Conditions
10%, V
A
= +V
DD
, V
B
= 0 V, –40 C < T
A
< +85 C unless
Min
–1
–0.5
–1
–0.5
–30
Typ
1
±
0.4
±
0.1
±
0.5
±
0.1
800
40
7
–1
–0.5
–1
–0.5
–2
0
0
10
48
7.5
2.4/2.1
Max
+1
+0.5
+1
+0.5
+30
100
Units
LSB
LSB
LSB
LSB
%
ppm/°C
Ω
Bits
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
nA
Symbol
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
R-DNL
R
WB
, V
A
= NC, R
AB
= 10 kΩ
Resistor Differential NL
2
R
WB
, V
A
= NC, R
AB
= 50 kΩ or 100 kΩ
R-INL
R
WB
, V
A
= NC, R
AB
= 10 kΩ
Resistor Nonlinearity
2
R
WB
, V
A
= NC, R
AB
= 50 kΩ or 100 kΩ
Nominal Resistor Tolerance
∆R
T
A
= +25°C
V
AB
= V
DD
, Wiper = No Connect
Resistance Temperature Coefficient
∆R
AB
/∆T
Wiper Resistance
R
W
I
W
= V
DD
/R, V
DD
= +3 V or +5 V
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution
N
3
INL
R
AB
= 10 kΩ
Integral Nonlinearity
R
AB
= 50 kΩ, 100 kΩ
DNL
R
AB
= 10 kΩ
Differential Nonlinearity Error
3
R
AB
= 50 kΩ, 100 kΩ
Code = 40
H
Voltage Divider Temperature Coefficient
∆V
W
/∆T
Code = 7F
H
Full-Scale Error
V
WFSE
Zero-Scale Error
V
WZSE
Code = 00
H
RESISTOR TERMINALS
Voltage Range
4
Capacitance
5
A, B
Capacitance
5
W
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Current
Input Capacitance
5
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation
6
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
5, 7, 8
Bandwidth –3 dB
V
A,
V
B,
V
W
C
A,
C
B
f = 1 MHz, Measured to GND, Code = 40
H
C
W
f = 1 MHz, Measured to GND, Code = 40
H
I
CM
V
A
= V
B
= V
W
V
IH
V
IL
I
IL
C
IL
V
DD
I
DD
P
DISS
PSS
BW_10K
BW_50K
BW_100K
THD
W
t
S
e
NWB
V
DD
= +5 V/+3 V
V
DD
= +5 V/+3 V
V
IN
= 0 V or +5 V
±
0.5
±
0.2
±
0.4
±
0.1
20
–0.5
+0.5
+1
+0.5
+1
+0.5
0
+1
V
DD
5
2.7
V
IH
= +5 V or V
IL
= 0 V, V
DD
= +5 V
V
IH
= +5 V or V
IL
= 0 V, V
DD
= +5 V
15
75
0.004
650
142
69
0.002
0.6/3/6
14
25
20
20
10
V
0.8/0.6 V
±
1
µA
pF
5.5
40
200
0.015
V
µA
µW
%/%
kHz
kHz
kHz
%
µs
nV/√Hz
ns
ns
ns
ns
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage
R
AB
= 10 kΩ, Code = 40
H
R
AB
= 50 kΩ, Code = 40
H
R
AB
= 100 kΩ, Code = 40
H
V
A
=1 V rms + 2.5 V dc, V
B
= 2.5 V dc, f = 1 kHz
V
A
= V
DD
, V
B
= 0 V, 50% of Final Value,
10K/50K/100K
R
WB
= 5 kΩ, f = 1 kHz
INTERFACE TIMING CHARACTERISTICS Applies to All Parts
5, 9
Input Clock Pulsewidth
t
CH
, t
CL
Clock Level High or Low
CS
to CLK Setup Time
t
CSS
CS
Rise to Clock Hold Time
t
CSH
U/D to Clock Fall Setup Time
t
UDS
NOTES
1
Typicals represent average readings at +25°C and V
DD
= +5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit.
3
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of
±
1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit.
4
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
5
Guaranteed by design and not subject to production test.
6
P
DISS
is calculated from (I
DD
×
V
DD
). CMOS logic level inputs result in minimum power dissipation.
7
Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-
width. The highest R value results in the minimum overall power consumption.
8
All dynamic characteristics use V
DD
= +5 V.
9
See timing diagrams for location of measured values. All input control voltages are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both V
DD
= +3 V or +5 V.
Specifications subject to change without notice.
–2–
REV. 0
AD5220
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C, unless otherwise noted)
PIN CONFIGURATION
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
V
A
, V
B
, V
W
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
DD
A
X
–B
X
, A
X
–W
X
, B
X
–W
X
. . . . . . . . . . . . . . . . . . . . . .
±
20 mA
Digital Input Voltage to GND . . . . . . . . . . . 0 V, V
DD
+ 0.3 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (T
J
MAX) . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . . . (T
J
max–T
A
)/θ
JA
Thermal Resistance
θ
JA
P-DIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103°C/W
SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
µSOIC
(RM-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CLK
1
U/D
2
8
V
DD
7
CS
AD5220
TOP VIEW
A1
3
(Not to Scale)
6
B1
5
W1
GND
4
PIN FUNCTION DESCRIPTIONS
Pin
No.
1
2
3
4
5
6
7
8
Name
CLK
U/D
A1
GND
W1
B1
CS
V
DD
Description
Serial Clock Input, Negative Edge Triggered
UP/DOWN Direction Increment Control
Terminal A1
Ground
Wiper Terminal
Terminal B1
Chip Select Input, Active Low
Positive Power Supply
Table I. Truth Table
CS
L
L
H
CLK
t
t
X
U/D
H
L
X
Operation
Wiper Increment Toward Terminal A
Wiper Decrement Toward Terminal B
Wiper Position Fixed
1
CS
0
t
CSS
t
CL
t
CH
1
CLK
0
1
U/D
0
t
CSH
t
UDS
Figure 3. Detail Timing Diagram
ORDERING GUIDE
Model
AD5220BN10
AD5220BR10
AD5220BRM10
AD5220BN50
AD5220BR50
AD5220BRM50
AD5220BN100
AD5220BR100
AD5220BRM100
k
10
10
10
50
50
50
100
100
100
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Descriptions
8-Lead Plastic DIP
8-Lead (SOIC)
8-Lead
µSOIC
8-Lead Plastic DIP
8-Lead (SOIC)
8-Lead
µSOIC
8-Lead Plastic DIP
8-Lead (SOIC)
8-Lead
µSOIC
Package Options
N-8
SO-8
RM-8
N-8
SO-8
RM-8
N-8
SO-8
RM-8
NOTE
The AD5220 die size is 37 mil
×
54 mil, 1998 sq mil; 0.938 mm
×
1.372 mm, 1.289 sq mm. Contains 754 transistors. Patent Number 5495245 applies.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5220 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD5220–Typical Performance Characteristics
100
PERCENT OF NOMINAL
END-TO-END RESISTANCE – % R
AB
6
V
DD
= 5.5V
R
AB
= 50k
48
SS = 300 UNITS
V
DD
= +2.7V
T
A
= +25 C
5
40
75
FREQUENCY
4
V
WB
– V
32
50
3
24
2
7F
H
40
H
08
H
20
H
10
H
04
H
02
H
01
H
16
25
1
8
0
R
WB
0
0
32
R
WA
0
64
96
CODE – Decimal
128
0
40
60
80
100
20
CONDUCTION CURRENT, I
WB
– A
120
20
28
36
44
52
WIPER RESISTANCE –
60
Figure 4. Wiper to End Terminal
Resistance vs. Code
Figure 5. Resistance Linearity vs.
Conduction Current
Figure 6. Wiper Contact Resistance
0.5
0.4
0.3
0.2
50k
VERSION
100k
VERSION
T
A
= +25 C
V
DD
= +5.5V
0.5
0.4
0.3
0.2
100k
VERSION
50k
VERSION
T
A
= +25 C
V
DD
= +5.5V
0.5
0.4
0.3
0.2
INL – LSB
10k
VERSION
50k
VERSION
RDNL – LSB
RINL – LSB
0.1
0.0
–0.1
–0.2
–0.3
10k
–0.4
–0.5
0
16
32
48
64
80 96
CODE – Decimal
112 128
VERSION
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
16
32
48
64
80 96
CODE – Decimal
112 128
10k
VERSION
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
16
32
48
64
80 96
CODE – Decimal
112 128
T
A
= +25 C
V
DD
= +5.5V
V
A
= +5.5V
V
B
= 0V
100k
VERSION
Figure 7. R-DNL Relative Resistance
Step Position Nonlinearity Error vs.
Code
Figure 8. R-INL Resistance Non-
linearity Error vs. Supply Voltage
Figure 9. Potentiometer Divider INL
Error vs. Code
0.5
0.4
0.3
0.2
100k
VERSION
50k
VERSION
T
A
= +25 C
V
DD
= +5.5V
V
A
= +5.5V
V
B
= 0V
0.600
0.525
POTENTIOMETER DIVIDER
NONLINEARITY – LSB
NOMINAL END-TO-END RESISTANCE – k
100
CODE = 40
H
R
AB
= 50k
V
A
= V
DD
100k
80
VERSION
0.450
0.375
0.300
0.255
0.150
0.075
0.000
2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00
SUPPLY VOLTAGE – V
DNL – LSB
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
16
10k
32
VERSION
60
40
50k
VERSION
20
10k
0
–40
VERSION
48
64
80 96
CODE – Decimal
112 128
–15
10
35
60
TEMPERATURE – C
85
Figure 10. Potentiometer Divider
DNL Error vs. Code
Figure 11. Potentiometer Divider
INL Error vs. Supply Voltage
Figure 12. Nominal Resistance vs.
Temperature
–4–
REV. 0
AD5220
POTENTIOMETER MODE TEMPCO – ppm/ C
60
RHEOSTAT MODE TEMPCO – ppm/ C
60
–55 C < T
A
< +85 C
V
DD
= +5.5V
53
46
39
32
25
18
11
4
–3
–10
0
16
32
48
64
80 96
CODE – Decimal
112 128
50k
AND 100k
VERSION
GAIN – dB
6
53
46
39
10k
32
25
18
11
4
–3
–10
0
16
32
50k
AND 100k
VERSION
–55 C < T
A
< +85 C
V
DD
= +5.5V
R
WB
MEASURED
V
A
= NO CONNECT
10k
VERSION
0
–6
–12
–18
–24
–30
–36
–42
–48
DATA = 40
H
V
DD
= +5V
V
IN
= VA = 100mV rms
V
B
= +2.5V
–
A
B
W
+
2.5V
–
+
OP42
00
H
40
H
20
H
10
H
08
H
04
H
02
H
01
H
VERSION
48
64
80 96
CODE – Decimal
112 128
–54
1k
10k
100k
FREQUENCY – Hz
1M
Figure 13.
∆
V
WB
/
∆
T Potentiometer
Mode Tempco (10 k
Ω
and 50 k
Ω
)
Figure 14.
∆
R
WB
/
∆
T Rheostat
Figure 15. 10 k
Ω
Gain vs. Frequency
vs. Code
6
0
–6
–12
GAIN – dB
00
H
40
H
20
H
GAIN – dB
6
0
–6
–12
–18
–24
–30
–36
–42
–48
DATA = 40
H
V
DD
= +5V
V
IN
= VA = 100mV rms
V
B
= +2.5V
A
B
W
+
2.5V
–
–
+
OP42
00
H
40
H
20
H
10
H
08
H
04
H
02
H
01
H
V
WB
V
DD
= +5.5V
V
A
= V
B
= 0V
f = 100kHz
20mV/
DIV
–18
–24
–30
–36
–42
–48
DATA = 40
H
V
DD
= +5V
V
IN
= VA = 100mV rms
V
B
= +2.5V
A
B
–
W +
+
2.5V
–
10
H
08
H
04
H
02
H
01
H
OP42
–54
1k
10k
100k
FREQUENCY – Hz
1M
–54
1k
10k
100k
FREQUENCY – Hz
1M
TIME 2 s / DIV
Figure 16. 50 k
Ω
Gain vs. Frequency
vs. Code
Figure 17. 100 k
Ω
Gain vs. Fre-
quency vs. Code
Figure 18. Digital Feedthrough
1.00
NORMALIZED GAIN FLATNESS – dB
–5.8
0.10
THD + NOISE – %
150mV
V
WB
100mV
50mV
V
DD
= +5.5V DATA
V
A
= +5.5V 40
H
v
3F
H
V
B
= 0V
f = 100kHz
0mV
T
A
= +25 C
V
DD
= +5.0V
OFFSET GND = +2.5V
R
AB
= 10k
–5.9
–6.0
–6.1
–6.2
–6.3
–6.4
–6.5
–6.6
–6.7
–6.8
10
100
A
B
10k
50k
100k
0.01
NONINVERTING
TEST CKT 32
DATA = 40
H
V
DD
= +5V
V
IN
= V
A
= 50mV rms
V
B
= +2.5V
–
W +
+
2.5V
–
0.001
5V
0V
OP42
INVERTING
TEST CKT 31
0.0001
10
100
1k
10k
FREQUENCY – Hz
100k
CLK
TIME 500ns / DIV
1k
10k
100k
FREQUENCY – Hz
1M
Figure 19. Midscale Transition Glitch
Figure 20. Total Harmonic Distortion
Plus Noise vs. Frequency
Figure 21. Normalized Gain Flatness
vs. Frequency
REV. 0
–5–
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