AGLP060V5-FVQG176 datasheet, PDF

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AGLP060V5-FVQG176: Descriptionfpga - field programmable gate array 60k system gates igloo plus; CategoryProgrammable logic devices Programmable logic; File Size4MB，128 Pages; ManufacturerActel; Websitehttp://www.actel.com/; Environmental Compliance

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AGLP060V5-FVQG176 Overview

fpga - field programmable gate array 60k system gates igloo plus

AGLP060V5-FVQG176 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Actel
package instruction	20 X 20 MM, 1 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, VQFP-176
Reach Compliance Code	compliant
maximum clock frequency	250 MHz
JESD-30 code	S-PQFP-G176
length	20 mm
Configurable number of logic blocks	1584
Equivalent number of gates	60000
Number of entries	137
Number of logical units	1584
Output times	137
Number of terminals	176
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1584 CLBS, 60000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	TFQFP
Encapsulate equivalent code	TQFP176,.87SQ,16
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.4 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	20 mm

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Revision 11

IGLOO PLUS Low Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

•

1.2 V to 1.5 V Core Voltage Support for Low Power

Supports Single-Voltage System Operation

5 µW Power Consumption in Flash*Freeze Mode

Low Power Active FPGA Operation

Flash*Freeze

Technology

Enables

Ultra-Low

Power

Consumption while Maintaining FPGA Content

• Configurable Hold Previous State, Tristate, HIGH, or LOW State

per I/O in Flash*Freeze Mode

• Easy Entry To / Exit From Ultra-Low Power Flash*Freeze Mode

Advanced I/O

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—4 Banks per Chip on All

IGLOO

PLUS Devices

• Single-Ended

I/O

Standards:

LVTTL,

LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V

• Selectable Schmitt Trigger Inputs

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Small-Footprint Packages across the IGLOO

PLUS Family

†

• Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,

and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

Feature Rich

• 30 k to 125 k System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 212 User I/Os

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal, Flash-Based CMOS Process

Live-at-Power-Up (LAPU) Level 0 Support

Single-Chip Solution

Retains Programmed Design When Powered Off

250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System

Performance

Clock Conditioning Circuit (CCC) and PLL

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

†

• FlashLock

to Secure FPGA Contents

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

• True Dual-Port SRAM (except ×18)

†

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Table 1 • IGLOO PLUS Product Family

IGLOO PLUS Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM Kbits (1,024 bits)

4,608-Bit Blocks

Secure (AES) ISP

FlashROM Kbits

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

AGLP030

30,000

256

792

–

120

CS201, CS289

VQ128

AGLP060

60,000

512

1,584

Yes

AGLP125

125,000

1,024

3,120

Yes

212

157

CS201, CS289

VQ176

CS281, CS289

Notes:

1. AGLP060 in CS201 does not support the PLL.

2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.

† The AGLP030 device does not support this feature.

June 2010

IGLOO PLUS Low Power Flash FPGAs

Table of Contents

IGLOO PLUS Device Family Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

IGLOO PLUS DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-77

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78

Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79

Package Pin Assignments

128-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

176-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

201-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

281-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

289-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

R ev i si o n 1 1

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