AD9868BCPZ datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > AD9868BCPZ

Preview

AD9868BCPZ: Descriptionbroadband modem mixed-signal front end; File Size568KB，36 Pages; ManufacturerADI; Websitehttps://www.analog.com

Download Datasheet Compare View All

AD9868BCPZ Overview

broadband modem mixed-signal front end

Preview

Download Datasheet

View All

Broadband Modem Mixed-Signal Front End

AD9868

FEATURES

Low cost 3.3 V CMOS MxFE for broadband modems

10-bit DAC converter

2×/4× interpolation filter

200 MSPS DAC update rate

Integrated 17 dBm line driver with 19.5 dB gain control

10-bit, 80 MSPS, ADC converter

−12 dB to +48 dB low noise RxPGA (<3 nV/√Hz)

Third-order, programmable low-pass filter

Flexible digital data path interface

Half- and full-duplex operation

Pin compatible with the AD9865

Various power-down/reduction modes

Internal clock multiplier (PLL)

2 auxiliary programmable clock outputs

Available in a 64-lead LFCSP_VQ

FUNCTIONAL BLOCK DIAGRAM

IOUTP+

IOUTP–

AD9868

PWRDWN

MODE

TXEN/TXSYNC

TXCLK/TXQUIET

ADIO[9:4]/

Tx[5:0]

2-4X

TxDAC

0 TO –7.5dB

IAMP

0 TO –12dB

IOUTN+

IOUTN–

CLK

SYNC.

CLK

MULTIPLIER

CLKOUT1

CLKOUT2

OSCIN

XTAL

ADIO[3:0]/

Rx[5:0]

RXEN/RXSYNC

RXCLK

AGC[5:0]

PORT

SPI

PORT

06733-001

ADC

80MSPS

0 TO 6dB

2-POLE

LPF

RX+

1-POLE

LPF

APPLICATIONS

Broadband wireline networking

RX–

= 1dB

CONTROL

–6 TO +18dB –6 TO +24dB

= 6dB

Figure 1.

GENERAL DESCRIPTION

The AD9868 is a mixed-signal front-end (MxFE®) IC for

transceiver applications requiring Tx path and Rx path

functionality with data rates up to 80 MSPS. A lower cost, pin-

compatible version of the

AD9865,

the AD9868 removes the

current amplifier (IAMP) IOUTP functionality and limits the

PLL VCO operating range of 80 MHz to 200 MHz.

The part is well-suited for half- and full-duplex applications.

The digital interface is extremely flexible, allowing simple

interfacing to digital back ends that support half- or full-duplex

data transfers, often allowing the AD9868 to replace discrete

ADC and DAC solutions. Power-saving modes include the

ability to reduce power consumption of individual functional

blocks or power down unused blocks in half-duplex applications.

A serial port interface (SPI) allows software programming of

the various functional blocks. An on-chip PLL clock multiplier

and synthesizer provide all the required internal clocks, as well

as two external clocks, from a single crystal or clock source.

The Tx signal path consists of a 2×/4× low-pass interpolation

filter, a 10-bit TxDAC, and a line driver. The transmit path

signal bandwidth can be as high as 34 MHz at an input data rate

of 80 MSPS. The TxDAC provides differential current outputs

that can be steered directly to an external load or to an internal

low distortion current amplifier (IAMP) capable of delivering

17 dBm peak signal power. Tx power can be digitally controlled

over a 19.5 dB range in 0.5 dB steps.

The receive path consists of a programmable amplifier

(RxPGA), a tunable low-pass filter (LPF), and a 10-bit ADC.

The low noise RxPGA has a programmable gain range of

−12 dB to +48 dB in 1 dB steps. Its input referred noise is less

than 3 nV/√Hz for gain settings beyond 36 dB. The receive path

LPF cutoff frequency can be set over a 15 MHz to 35 MHz

range or it can be simply bypassed. The 10-bit ADC achieves

excellent dynamic performance up to an 80 MSPS span. Both

the RxPGA and the ADC offer scalable power consumption

allowing power/performance optimization.

The AD9868 provides a highly integrated solution for many

broadband modems. It is available in a space-saving package, a

16-lead LFCSP, and is specified over the commercial temperature

range (−40°C to +85°C).

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

AD9868

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Tx Path Specifications.................................................................. 3

Rx Path Specifications.................................................................. 4

Power Supply Specifications........................................................ 6

Digital Specifications ................................................................... 7

Serial Port Timing Specifications ............................................... 7

Half-Duplex Data Interface (ADIO Port) Timing

Specifications ................................................................................ 8

Full-Duplex Data Interface (Tx and Rx Port) Timing

Specifications ................................................................................ 8

Absolute Maximum Ratings............................................................ 9

Thermal Characteristics .............................................................. 9

Explanation of Test Levels ........................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Serial Port ........................................................................................ 12

Serial Port Interface (SPI).......................................................... 14

Digital Interface .............................................................................. 16

Half-Duplex Mode ..................................................................... 16

Full-Duplex Mode ...................................................................... 17

RxPGA Control .......................................................................... 19

TxPGA Control .......................................................................... 20

Transmit Path.................................................................................. 21

Digital Interpolation Filters ...................................................... 21

TxDAC and IAMP Architecture .............................................. 22

Tx Programmable Gain Control .............................................. 23

TxDAC Output Operation........................................................ 23

IAMP Current-Mode Operation.............................................. 23

Receive Path .................................................................................... 24

Rx Programmable Gain Amplifier........................................... 24

Low-Pass Filter............................................................................ 25

Analog-to-Digital Converter (ADC)....................................... 26

AGC Timing Considerations.................................................... 27

Clock Synthesizer ........................................................................... 28

Power Control and Dissipation .................................................... 30

Power-Down ............................................................................... 30

Half-Duplex Power Savings ...................................................... 30

Power Reduction Options ......................................................... 31

Power Dissipation....................................................................... 33

Mode Select upon Power-Up and Reset.................................. 33

Analog and Digital Loopback Test Modes.............................. 34

Outline Dimensions ....................................................................... 35

Ordering Guide .......................................................................... 35

REVISION HISTORY

5/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 36

AD9868BCPZ Related Products

	AD9868BCPZ	AD9868	AD9868BCPZRL
Description	broadband modem mixed-signal front end	broadband modem mixed-signal front end	broadband modem mixed-signal front end

Recommended Resources

PLC light source robot hand bubble control circuit

DC converter output voltage

Low-cost HDTV satellite STB decoding circuit diagram designed by STi7111

Crystal diode three-phase bridge resistive load rectifier circuit

MAX759 forms the -24V power supply circuit diagram of LCD

Low light indicator circuit

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components