INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT175
Quad D-type flip-flop with reset;
positive-edge trigger
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
1998 Jul 08
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
FEATURES
•
Four edge-triggered D flip-flops
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT175 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
74HC/HCT175
The 74HC/HCT175 have four edge-triggered, D-type
flip-flops with individual D inputs and both Q and Q
outputs.
The common clock (CP) and master reset (MR) inputs load
and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Q
n
) of the flip-flop.
All Q
n
outputs will be forced LOW independently of clock
or data inputs by a LOW voltage level on the MR input.
The device is useful for applications where both the true
and complement outputs are required and the clock and
master reset are common to all storage elements.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
PARAMETER
propagation delay
CP to Q
n
, Q
n
MR to Q
n
t
PLH
propagation delay
CP to Q
n
, Q
n
MR to Q
n
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop notes 1 and 2
17
15
83
3.5
32
16
16
54
3.5
34
ns
ns
MHz
pF
pF
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
17
15
16
19
ns
ns
HCT
UNIT
1998 Jul 08
2
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
ORDERING INFORMATION
TYPE
NUMBER
74HC175N;
74HCT175N
74HC175D;
74HCT175D
74HC175DB;
74HCT175DB
74HC175PW;
74HCT175PW
PACKAGE
NAME
DIP16
SO16
SSOP16
TSSOP16
DESCRIPTION
plastic dual in-line package; 16 leads (300 mil); long body
plastic small outline package; 16 leads; body width 3.9 mm
74HC/HCT175
VERSION
SOT38-1
SOT109-1
SOT338-1
SOT403-1
plastic shrink small outline package; 16 leads; body width 5.3 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
PIN DESCRIPTION
PIN NO.
1
2, 7, 10, 15
3, 6, 11, 14
4, 5, 12, 13
8
9
16
SYMBOL
MR
Q
0
to Q
3
Q
0
to Q
3
D
0
to D
3
GND
CP
V
CC
NAME AND FUNCTION
master reset input (active LOW)
flip-flop outputs
complementary flip-flop outputs
data inputs
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jul 08
3
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74HC/HCT175
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
OPERATING MODES
MR
reset (clear)
load “1”
load “0”
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
↑
= LOW-to-HIGH CP transition
X = don’t care
L
H
H
CP
X
↑
↑
D
n
X
h
I
Q
n
L
H
L
Q
n
H
L
H
OUTPUTS
Fig.5 Logic diagram.
1998 Jul 08
4
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
, Q
n
propagation delay
MR to Q
n
, Q
n
output transition time
+25
typ.
55
20
16
t
PHL
/ t
PLH
50
18
14
t
THL
/ t
TLH
19
7
6
t
W
clock pulse width
HIGH or LOW
80
16
14
t
W
master reset pulse width 80
LOW
16
14
t
rem
removal time
MR to CP
5
5
5
t
su
set-up time
D
n
to CP
hold time
CP to D
n
maximum clock pulse
frequency
80
16
14
t
h
25
5
4
f
max
6.0
30
35
22
8
6
19
7
6
−33
−12
−10
3
1
1
2
0
0
25
75
89
−40
to
+85
max. min.
175
35
30
150
30
26
75
15
13
100
20
17
100
20
17
5
5
5
100
20
17
30
6
5
4.8
24
28
max.
220
44
37
190
38
33
95
19
16
120
24
20
120
24
20
5
5
5
120
24
20
40
8
7
4.0
20
24
ns
ns
ns
ns
−40
to
+125
min.
max.
265
53
45
225
45
38
110
22
19
ns
ns
ns
ns
74HC/HCT175
TEST CONDITIONS
UNIT
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
MHz
2.0
4.5
6.0
Fig.6
Fig.7
Fig.7
Fig.8
Fig.8
Fig.6
Fig.6
Fig.8
WAVEFORMS
Fig.6
1998 Jul 08
5
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