Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5200BDS
Rev. 4, 02/2010
MPC5200B Data Sheet
Key features are shown below.
• MPC603e series e300 core
– Superscalar architecture
– 760 MIPS at 400 MHz (–40
o
C to +85
o
C)
– 16 KB Instruction cache, 16 KB Data cache
– Double precision FPU
– Instruction and Data MMU
– Standard and Critical interrupt capability
• SDRAM / DDR Memory Interface
– Up to 133 MHz operation
– SDRAM and DDR SDRAM support
– 256 MB addressing range per CS, two CS available
– 32-bit data bus
– Built-in initialization and refresh
• Flexible multi-function External Bus Interface
– Supports interfacing to ROM/Flash/SRAM memories or
other memory mapped devices
– 8 programmable Chip Selects
– Non-multiplexed data access using 8-/16-/32-bit databus
with up to 26-bit address
– Short or Long Burst capable
– Multiplexed data access using 8-/16-/32-bit databus
with up to 25-bit address
• Peripheral Component Interconnect (PCI) Controller
– Version 2.2 PCI compatibility
– PCI initiator and target operation
– 32-bit PCI Address/Data bus
– 33 and 66 MHz operation
– PCI arbitration function
• ATA Controller
– Version 4 ATA compatible external interface—IDE Disk
Drive connectivity
• BestComm DMA subsystem
– Intelligent virtual DMA Controller
– Dedicated DMA channels to control peripheral
reception and transmission
– Local memory (SRAM 16 KB)
• 6 Programmable Serial Controllers (PSC)
– UART or RS232 interface
– CODEC interface for Soft Modem, Master/Slave
CODEC Mode, I
2
S and AC97
TEPBGA–272
27 mm x 27 mm
•
•
•
•
•
•
•
•
•
•
•
•
– Full duplex SPI mode
– IrDA mode from 2400 bps to 4 Mbps
Fast Ethernet Controller (FEC)
– Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE
802.3 MII, 10 Mbps 7-wire interface
Universal Serial Bus Controller (USB)
– USB Revision 1.1 Host
– Open Host Controller Interface (OHCI)
– Integrated USB Hub, with two ports.
Two Inter-Integrated Circuit Interfaces (I
2
C)
Serial Peripheral Interface (SPI)
Dual CAN 2.0 A/B Controller (MSCAN)
– Implementation of version 2.0A/B CAN protocol
– Standard and extended data frames
J1850 Byte Data Link Controller (BDLC)
J1850 Class B data communication network interface
compatible and ISO compatible for low speed (<125 kbps)
serial data communications in automotive applications.
Supports 4X mode, 41.6 kbps
In-frame response (IFR) types 0, 1, 2, and 3 supported
Systems level features
– Interrupt Controller supports four external interrupt
request lines and 47 internal interrupt sources
– GPIO/Timer functions
Up to 56 total GPIO pins that support a variety of
interrupt/WakeUp capabilities.
Eight GPIO pins with timer capability supporting input
capture, output compare, and pulse width modulation
(PWM) functions
– Real-time Clock with one-second resolution
– Systems Protection (watch dog timer, bus monitor)
– Individual control of functional block clock sources
– Power management: Nap, Doze, Sleep, Deep Sleep
modes
– Support of WakeUp from low power modes by different
sources (GPIO, RTC, CAN)
Test/Debug features
– JTAG (IEEE 1149.1 test access port)
– Common On-chip Processor (COP) debug port
On-board PLL and clock generation
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2008, 2010. All rights reserved.
Table of Contents
1
Electrical and Thermal Characteristics . . . . . . . . . . . . . . . . . . .4
1.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .4
1.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . .4
1.1.2 Recommended Operating Conditions . . . . . . . . .4
1.1.3 DC Electrical Specifications. . . . . . . . . . . . . . . . .5
1.1.4 Electrostatic Discharge . . . . . . . . . . . . . . . . . . . .7
1.1.5 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . .7
1.1.6 Thermal Characteristics. . . . . . . . . . . . . . . . . . . .9
1.2 Oscillator and PLL Electrical Characteristics . . . . . . . .10
1.2.1 System Oscillator Electrical Characteristics . . .11
1.2.2 RTC Oscillator Electrical Characteristics . . . . . .11
1.2.3 System PLL Electrical Characteristics. . . . . . . .11
1.2.4 e300 Core PLL Electrical Characteristics . . . . .11
1.3 AC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .12
1.3.1 AC Test Timing Conditions: . . . . . . . . . . . . . . . .12
1.3.2 AC Operating Frequency Data. . . . . . . . . . . . . .13
1.3.3 Clock AC Specifications. . . . . . . . . . . . . . . . . . .13
1.3.4 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.3.5 External Interrupts . . . . . . . . . . . . . . . . . . . . . . .15
1.3.6 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.3.7 PCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.3.8 Local Plus Bus . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.3.9 ATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.3.10 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
1.3.11 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
1.3.12 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
1.3.13 MSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
1.3.14 I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
1.3.15 J1850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1.3.16 PSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
1.3.17 GPIOs and Timers . . . . . . . . . . . . . . . . . . . . . . 54
1.3.18 IEEE 1149.1 (JTAG) AC Specifications . . . . . . 56
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.2 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . 58
2.3 Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
System Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.1 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . . 64
3.1.1 Power Up Sequence. . . . . . . . . . . . . . . . . . . . . 65
3.1.2 Power Down Sequence . . . . . . . . . . . . . . . . . . 65
3.2 System and CPU Core AVDD Power Supply Filtering. 65
3.3 Pull-up/Pull-down Resistor Requirements . . . . . . . . . . 65
3.3.1 Pull-down Resistor Requirements for TEST pins65
3.3.2 Pull-up Requirements for the PCI Control Lines 66
3.3.3 Pull-up/Pull-down Requirements for MEM_MDQS
Pins (SDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.3.4 .Pull-up/Pull-down Requirements for MEM_MDQS
Pins (DDR 16-bit Mode) . . . . . . . . . . . . . . . . . . 66
3.4 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.4.1 JTAG_TRST . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.4.2 e300 COP/BDM Interface . . . . . . . . . . . . . . . . 67
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2
3
4
5
MPC5200B Data Sheet, Rev. 4
2
Freescale Semiconductor
Figure 1
shows a simplified MPC5200B block diagram.
SDRAM/DDR
Freescale Semiconductor
MPC5200B Data Sheet, Rev. 4
3
Systems Interface Unit (SIU)
Real-Time Clock
SDRAM/DDR
Memory Controller
603
e300 Core
System Functions
Interrupt Controller
GPIO/Timers
Local Plus Controller
JTAG / COP
Interface
Reset / Clock
Generation
SRAM
16 KB
BestComm
DMA
PCI Bus Controller
Local
Bus
ATA Host Controller
CommBus
PSC
6x
Ethernet
I
2
C
2x
SPI
USB
2x
J1850
MSCAN
2x
Figure 1. Simplified Block Diagram—MPC5200B
1
1.1
1.1.1
Electrical and Thermal Characteristics
DC Electrical Characteristics
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings
(1)
Characteristic
Supply voltage — e300 core and peripheral logic
Supply voltage — I/O buffers
Supply voltage — System APLL
Supply voltage — e300 APLL
Input voltage (VDD_IO)
Input voltage (VDD_MEM_IO)
Input voltage overshoot
Input voltage undershoot
Storage temperature range
1
The tables in this section describe the MPC5200B DC Electrical characteristics.
Table 1
gives the absolute maximum ratings.
Sym
VDD_CORE
VDD_IO,
VDD_MEM_IO
SYS_PLL_AVDD
CORE_PLL_AVDD
Vin
Vin
Vinos
Vinus
Tstg
Min
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
—
—
–55
Max
1.8
3.6
2.1
2.1
VDD_IO + 0.3
VDD_MEM_IO
+ 0.3
1.0
1.0
150
Unit
V
V
V
V
V
V
V
V
o
C
SpecID
D1.1
D1.2
D1.3
D1.4
D1.5
D1.6
D1.7
D1.8
D1.9
Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed.
Stresses beyond those listed may affect device reliability or cause permanent damage.
1.1.2
Recommended Operating Conditions
Table 2. Recommended Operating Conditions
Characteristic
Sym
VDD_CORE
VDD_IO
VDD_MEM_IO
SDR
VDD_MEM_IO
DDR
SYS_PLL_AVDD
CORE_PLL_AVDD
Min
(1)
1.42
3.0
3.0
2.42
1.42
1.42
Max
(1)
1.58
3.6
3.6
2.63
1.58
1.58
Unit
V
V
V
V
V
V
SpecID
D2.1
D2.2
D2.3
D2.4
D2.5
D2.6
Table 2
gives the recommended operating conditions.
Supply voltage — e300 core and peripheral
logic
Supply voltage — standard I/O buffers
Supply voltage — memory I/O buffers (SDR)
Supply voltage — memory I/O buffers (DDR)
Supply voltage — System APLL
Supply voltage — e300 APLL
MPC5200B Data Sheet, Rev. 4
4
Freescale Semiconductor
Table 2. Recommended Operating Conditions (continued)
Characteristic
Input voltage — standard I/O buffers
Input voltage — memory I/O buffers (SDR)
Input voltage — memory I/O buffers (DDR)
Ambient operating temperature range
(2)
Die junction operating temperature range
1
Sym
Vin
Vin
SDR
Vin
DDR
T
A
Tj
Min
(1)
0
0
0
–40
–40
Max
(1)
VDD_IO
VDD_MEM_IO
SDR
VDD_MEM_IO
DDR
+85
+115
Unit
V
V
V
o
o
SpecID
D2.7
D2.8
D2.9
D2.10
D2.12
C
C
These are recommended and tested operating conditions. Proper device operation outside these conditions is not
guaranteed.
2
Maximum e300 core operating frequency is 400 MHz.
1.1.3
DC Electrical Specifications
Table 3. DC Electrical Specifications
Characteristic
Input high voltage
Input high voltage
Input high voltage
Input high voltage
Input high voltage
Input high voltage
Input low voltage
Input low voltage
Input low voltage
Input low voltage
Input low voltage
Input low voltage
Condition
Input type = TTL
VDD_IO/VDD_MEM_IO
SDR
Input type = TTL
VDD_MEM_IO
DDR
Input type = PCI
VDD_IO
Input type = SCHMITT
VDD_IO
SYS_XTAL_IN
RTC_XTAL_IN
Input type = TTL
VDD_IO/VDD_MEM_IO
SDR
Input type = TTL
VDD_MEM_IO
DDR
Input type = PCI
VDD_IO
Input type = SCHMITT
VDD_IO
SYS_XTAL_IN
RTC_XTAL_IN
Vin = 0 or
VDD_IO/VDD_IO_MEM
SDR
(depending on input type
(1)
)
Table 3
gives the DC Electrical characteristics for the MPC5200B at recommended operating conditions (see
Table 2).
Sym
V
IH
V
IH
V
IH
V
IH
CV
IH
CV
IH
V
IL
V
IL
V
IL
V
IL
CV
IL
CV
IL
I
IN
Min
2.0
1.7
2.0
2.0
2.0
2.0
—
—
—
—
—
—
—
Max
—
—
—
—
—
—
0.8
0.7
0.8
0.8
0.8
0.8
±2
Unit
V
V
V
V
V
V
V
V
V
V
V
V
μA
SpecID
D3.1
D3.2
D3.3
D3.4
D3.5
D3.6
D3.7
D3.8
D3.9
D3.10
D3.11
D3.12
D3.13
Input leakage current
Input leakage current
SYS_XTAL_IN
Vin = 0 or VDD_IO
I
IN
—
±10
μA
D3.14
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
5
京公网安备 11010802033920号
EEWORLD
