a
5 MHz–400 MHz 100 dB High Precision
Limiting-Logarithmic Amplifier
AD8306
FUNCTIONAL BLOCK DIAGRAM
SIX STAGES TOTAL GAIN 72dB
INHI
12dB
INLO
LADR ATTEN
4 DET
BIAS
CTRL
I–V
TEN DETECTORS SPACED 12dB
12dB
12dB
LIM
LMLO
LMDR
TYP GAIN 18dB
LMHI
FEATURES
Complete, Fully Calibrated Log-Limiting IF Amplifier
100 dB Dynamic Range: –91 dBV to +9 dBV
Stable RSSI Scaling Over Temperature and Supplies:
20 mV/dB Slope, –95 dBm Intercept
0.4 dB RSSI Linearity up to 200 MHz
Programmable Limiter Gain and Output Current
Differential Outputs to 10 mA, 2.4 V p-p
Overall Gain 90 dB, Bandwidth 400 MHz
Constant Phase (Typical 56 ps Delay Skew)
Single Supply of +2.7 V to +6.5 V at 16 mA Typical
Fully Differential Inputs, R
IN
= 1 k , C
IN
= 2.5 pF
500 ns Power-Up Time, <1 A Sleep Current
APPLICATIONS
Receivers for Frequency and Phase Modulation
Very Wide Range IF and RF Power Measurement
Receiver Signal Strength Indication (RSSI)
Low Cost Radar and Sonar Signal Processing
Instrumentation: Network and Spectrum Analyzers
PRODUCT DESCRIPTION
DET
DET
DET
VLOG
FLTR
ENBL
GAIN
BIAS
BAND-GAP
REFERENCE
SLOPE
BIAS
INTERCEPT
TEMP COMP
The AD8306 is a complete IF limiting amplifier, providing both
an accurate logarithmic (decibel) measure of the input signal
(the RSSI function) over a dynamic range of 100 dB, and a
programmable limiter output, useful from 5 MHz to 400 MHz.
It is easy to use, requiring few external components. A single
supply voltage of +2.7 V to +6.5 V at 16 mA is needed, corre-
sponding to a power consumption of under 50 mW at 3 V, plus
the limiter bias current, determined by the application and typi-
cally 2 mA, providing a limiter gain of 90 dB when using 200
Ω
loads. A CMOS-compatible control interface can enable the
AD8306 within about 500 ns and disable it to a standby current
of under 1
µA.
The six cascaded amplifier/limiter cells in the main path have a
small signal gain of 12.04 dB (×4), with a –3 dB bandwidth of
850 MHz, providing a total gain of 72 dB. The programmable
output stage provides a further 18 dB of gain. The input is fully
differential and presents a moderately high impedance (1 kΩ in
parallel with 2.5 pF). The input-referred noise-spectral-density,
when driven from a terminated 50
Ω,
source is 1.28 nV/√Hz,
equivalent to a noise figure of 3 dB. The sensitivity of the
AD8306 can be raised by using an input matching network.
Each of the main gain cells includes a full-wave detector. An
additional four detectors, driven by a broadband attenuator, are
used to extend the top end of the dynamic range by over 48 dB.
The overall dynamic range for this combination extends from
–91 dBV (–78 dBm at the 50
Ω
level) to a maximum permissible
value of +9 dBV, using a balanced drive of antiphase inputs each of
2 V in amplitude, which would correspond to a sine wave power
of +22 dBm if the differential input were terminated in 50
Ω.
Through laser trimming, the slope of the RSSI output is closely
controlled to 20 mV/dB, while the intercept is set to –108 dBV
(–95 dBm re 50
Ω).
These scaling parameters are determined
by a band-gap voltage reference and are substantially indepen-
dent of temperature and supply. The logarithmic law conform-
ance is typically within
±
0.4 dB over the central 80 dB of this
range at any frequency between 10 MHz and 200 MHz, and is
degraded only slightly at 400 MHz.
The RSSI response time is nominally 73 ns (10%–90%). The
averaging time may be increased without limit by the addition of
an external capacitor. The full output of 2.34 V at the maximum
input of +9 dBV can drive any resistive load down to 50
Ω
and
this interface remains stable with any value of capacitance on
the output.
The AD8306 is fabricated on an advanced complementary
bipolar process using silicon-on-insulator isolation techniques
and is available in the industrial temperature range of –40°C to
+85°C, in a 16-lead narrow body SO package. The AD8306 is
also available for the full military temperature range of –55°C to
+125°C, in a 16-lead side-brazed ceramic DIP.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD8306–SPECIFICATIONS
(V = +5 V, T = +25 C, f = 10 MHz, unless otherwise noted)
S
A
Parameter
INPUT STAGE
Maximum Input
2
Equivalent Power in 50
Ω
Noise Floor
Equivalent Power in 50
Ω
Input Resistance
Input Capacitance
DC Bias Voltage
LIMITING AMPLIFIER
Usable Frequency Range
At Limiter Output
Phase Variation at 100 MHz
Limiter Output Current
Versus Temperature
Input Range
3
Maximum Output Voltage
Rise/Fall Time (10%–90%)
LOGARITHMIC AMPLIFIER
±
3 dB Error Dynamic Range
Transfer Slope
4
Over Temperature
Intercept (Log Offset)
4
Over Temperature
Temperature Sensitivity
Linearity Error (Ripple)
Output Voltage
Conditions
(Inputs INHI, INLO)
Differential Drive, p-p
Terminated in 52.3
Ω
R
IN
Terminated 50
Ω
Source
400 MHz Bandwidth
From INHI to INLO
From INHI to INLO
Either Input
(Outputs LMHI, LMLO)
R
LOAD
= R
LIM
= 50
Ω,
to –10 dB Point
Over Input Range –73 dBV to –3 dBV
Nominally 400 mV/R
LIM
–40°C
≤
T
A
≤
+85°C
At Either LMHI or LMLO, wrt VPS2
R
LOAD
= 50
Ω,
40
Ω ≤
R
LIM
≤
400
Ω
(Output VLOG)
From Noise Floor to Maximum Input
f = 10 MHz
f = 100 MHz
–40°C < T
A
< +85°C
f = 10 MHz
f = 100 MHz
–40°C
≤
T
A
≤
+85°C
Input from –80 dBV to +0 dBV
Input = –91 dBV, V
S
= +5 V, +2.7 V
Input = +9 dBV, V
S
= +5 V
Input = –3 dBV, V
S
= +3 V
To Ground
Large Scale Input, +3 dBV, R
L
≥
50
Ω,
C
L
≤
100 pF
Large Scale Input, +3 dBV, R
L
≥
50
Ω,
C
L
≤
100 pF
Min
1
±
3.5
Typ
±
4
+9
+22
1.28
–78
1000
2.5
1.725
Max
1
Units
V
dBV
dBm
nV/√Hz
dBm
Ω
pF
V
MHz
MHz
Degrees
mA
%/°C
dBV
V
ns
800
1200
5
585
±
2
1
–0.008
1.25
0.6
100
20
19.6
20
–108
–108.4
–108
–0.009
±
0.4
0.34
2.34
2.10
50
1.0
0.3
3.5
120
73
5
16
16
0.01
2.0
40
1
207
400
0
–78
1
10
+9
19.5
19.3
–109.5
–111
Minimum Load Resistance, R
L
Maximum Sink Current
Output Resistance
Small-Signal Bandwidth
Output Settling Time to 2%
Rise/Fall Time (10%–90%)
POWER INTERFACES
Supply Voltage, V
S
Quiescent Current
Over Temperature
Disable Current
Additional Bias for Limiter
Logic Level to Enable Power
Input Current when HI
Logic Level to Disable Power
TRANSISTOR COUNT
40
0.75
dB
20.5
mV/dB
mV/dB
20.7
mV/dB
–106.5 dBV
dBV
–105
dBV
dB/°C
dB
V
2.75
V
V
Ω
1.25
mA
Ω
MHz
220
ns
100
ns
6.5
20
23
4
2.25
V
S
60
207
V
mA
mA
µA
mA
V
µA
V
Zero-Signal, LMDR Open
–40°C < T
A
< +85°C
–40°C < T
A
< +85°C
R
LIM
= 400
Ω
(See Text)
HI Condition, –40°C < T
A
< +85°C
3 V at ENBL, –40°C < T
A
< +85°C
LO Condition, –40°C < T
A
< +85°C
# of Transistors
2.7
13
11
2.7
–0.5
NOTES
1
Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values.
2
The input level is specified in “dBV” since logarithmic amplifiers respond strictly to voltage, not power. 0 dBV corresponds to a sinusoidal single-frequency input of
1 V rms. A power level of 0 dBm (1 mW) in a 50
Ω
termination corresponds to an input of 0.2236 V rms. Hence, in the special case of 50
Ω
termination, dBV values
can be converted into dBm by adding a fixed offset of +13 to the dBV rms value.
3
Due to the extremely high Gain Bandwidth Product of the AD8306, the output of either LMHI or LMLO will be unstable for levels below –78 dBV (–65 dBm, re 50
Ω).
4
Standard deviation remains essentially constant over frequency. See Figures 13, 14, 16 and 17.
Specifications subject to change without notice.
–2–
REV. A
AD8306
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 V
Input Level, Differential (re 50
Ω)
. . . . . . . . . . . . . . . +26 dBm
Input Level, Single-Ended (re 50
Ω)
. . . . . . . . . . . . . +20 dBm
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 800 mW
θ
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C/W
θ
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . +125°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range
–65°C to +150°C
Lead Temperature Range (Soldering 60 sec)
+300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may effect device reliability.
ORDERING GUIDE
Model
AD8306AR
AD8306AR-REEL
AD8306AR-REEL7
AD8306ACHIPS
5962-9864601QEA
AD8306-EVAL
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
Package
Description
16-Lead Narrow Body SO
13" Tape and Reel
7" Tape and Reel
Die
16-Lead Side-Brazed Ceramic DIP
Evaluation Board
Package
Options
SO-16
SO-16
SO-16
D-16
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8306 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
Pin
1
2
Name
Function
COM2
1
VPS1
2
PADL
3
INHI
4
16
VLOG
15
VPS2
14
PADL
COM2 Special Common Pin for RSSI Output.
VPS1
Supply Pin for First Five Amplifier Stages
and the Main Biasing System.
3, 6, 11, 14 PADL Four Tie-Downs to the Paddle on
which the IC Is Mounted; Grounded.
4
INHI
Signal Input, HI or Plus Polarity.
5
INLO Signal Input, LO or Minus Polarity.
7
COM1 Main Common Connection.
8
ENBL Chip Enable; Active When HI.
9
LMDR Limiter Drive Programming Pin.
10
FLTR RSSI Bandwidth-Reduction Pin.
12
LMLO Limiter Output, LO or Minus Polarity.
13
LMHI Limiter Output, HI or Plus Polarity.
15
VPS2
Supply Pin for Sixth Gain Stage, Limiter
and RSSI Output Stage Load Current.
16
VLOG Logarithmic (RSSI) Output.
AD8306
13
LMHI
TOP VIEW
INLO
5
(Not to Scale)
12
LMLO
PADL
6
COM1
7
ENBL
8
11
PADL
10
FLTR
9
LMDR
REV. A
–3–
AD8306–Typical Performance Characteristics
100
10
SUPPLY CURRENT – mA
VLOG
500mV PER
VERTICAL
DIVISION
1
T
A
= +25 C
0.1
T
A
= +85 C
0.01
T
A
= –40 C
GROUND REFERENCE
INPUT LEVEL
SHOWN IS –3dBV
0.001
INPUT
1V PER
VERTICAL
DIVISION
0.0001
0.00001
0.5
100ns PER HORIZONTAL DIVISION
0.7
0.9
1.1
1.3
1.5
1.7
1.9
ENABLE VOLTAGE – V
2.1
2.3
2.5
Figure 1. Supply Current vs. Enable Voltage @
T
A
= –40
°
C, +25
°
C and +85
°
C
Figure 4. RSSI Pulse Response for Inputs Stepped from
Zero to –83 dBV, –63 dBV, –43 dBV, –23 dBV, –3 dBV
14
12
SUPPLY CURRENT – mA
10
ADDITIONAL SUPPLY CURRENT
8
6
500mV PER
VERTICAL
DIVISION
VLOG
GROUND REFERENCE
INPUT
4
LIMITER OUTPUT
CURRENT
100ns PER HORIZONTAL DIVISION
2
0
0
2V PER
VERTICAL
DIVISION
50
100
150
200
250
R
LIM
–
300
350
400
450
Figure 2. Additional Supply Current and Limiter Output
Current vs. R
LIM
Figure 5. Large Signal RSSI Pulse Response with R
L
= 100
Ω
and C
L
= 33 pF, 100 pF and 330 pF (Overlapping Curves)
27pF
270pF
VLOG
500mV PER
VERTICAL
DIVISION
VLOG
200mV PER
VERTICAL
DIVISION
3300pF
GROUND REFERENCE
INPUT
2V PER
VERTICAL
DIVISION
100ns PER HORIZONTAL DIVISION
100 s PER HORIZONTAL DIVISION
GROUND REFERENCE
Figure 3. Large Signal RSSI Pulse Response with
C
L
= 100 pF and R
L
= 50
Ω
and 75
Ω
(Curves Overlap)
Figure 6. Small Signal AC Response of RSSI Output with
External Filter Capacitance of 27 pF, 270 pF and 3300 pF
–4–
REV. A
AD8306
2.5
5
4
2
3
2
RSSI OUTPUT – V
ERROR – dB
1.5
1
0
–1
–2
–3
T
A
= +85 C
1
T
A
= +85 C
0.5
T
A
= –40 C
–80
–60
–40
–20
0
(+13dBm)
T
A
= +25 C
T
A
= –40 C
–4
–5
–120
T
A
= +25 C
0
–120
–100
(–87dBm)
20
–100
(–87dBm)
–80
–60
–40
–20
0
(+13dBm)
20
INPUT LEVEL – dBV
INPUT LEVEL – dBV
Figure 7. RSSI Output vs. Input Level, 100 MHz Sine In-
put, at T
A
= –40
°
C, +25
°
C and +85
°
C, Single-Ended Input
Figure 10. Log Linearity of RSSI Output vs. Input Level,
100 MHz Sine Input, at T
A
= –40
°
C, +25
°
C, and +85
°
C
2.5
100MHz
5
4
DYNAMIC RANGE
10MHz
50MHz
100MHz
1dB
86
90
96
3dB
93
97
100
2
50MHz
3
10MHz
RSSI OUTPUT – V
2
ERROR – dB
1.5
1
100MHz
0
10MHz
–1
–2
50MHz
1
0.5
–3
–4
0
–120
–100
(–87dBm)
–80
–60
–40
–20
0
(+13dBm)
20
–5
–120
–100
(–87dBm)
–80
–60
–40
–20
0
(+13dBm)
20
INPUT LEVEL – dBV
INPUT LEVEL – dBV
Figure 8. RSSI Output vs. Input Level, at T
A
= +25
°
C, for
Frequencies of 10 MHz, 50 MHz and 100 MHz
Figure 11. Log Linearity of RSSI Output vs. Input Level, at
T
A
= +25
°
C, for Frequencies of 10 MHz, 50 MHz and 100 MHz
2.5
200MHz
5
4
DYNAMIC RANGE
200MHz
300MHz
400MHz
1dB
96
90
85
3dB
100
100
100
2
400MHz
3
2
RSSI OUTPUT – V
ERROR – dB
1.5
300MHz
1
0
–1
–2
400MHz
300MHz
200MHz
1
0.5
–3
–4
0
–120
–100
(–87dBm)
–80
–60
–40
–20
0
(+13dBm)
20
–5
–120
–100
(–87dBm)
–80
–60
–40
–20
0
(+13dBm)
20
INPUT LEVEL – dBV
INPUT LEVEL – dBV
Figure 9. RSSI Output vs. Input Level, at T
A
= +25
°
C, for
Frequencies of 200 MHz, 300 MHz and 400 MHz
Figure 12. Log Linearity of RSSI Output vs. Input Level,
at T
A
= +25
°
C, for Frequencies of 200 MHz, 300 MHz and
400 MHz
REV. A
–5–
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