perature Range unless otherwise noted. See Note 1 for supply variations.)
CC
Conditions
Min
Typ
Max
Units
Integral Linearity “G”
Integral Linearity “G”
Differential Linearity “G”
Differential Linearity “G”
Integral Linearity “F”
Integral Linearity “F”
Differential Linearity “F”
Differential Linearity “F”
Zero Scale Error
Zero Scale Drift
Gain Error
Gain Drift
REFERENCE
2
Reference Input Current
OUTPUT CHARACTERISTICS
Output Current
Output Capacitance
Settling Time
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Logic Input Current
Logic Input Current
Input Capacitance
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation
INL
INL
DNL
DNL
INL
INL
DNL
DNL
ZSE
TC
ZSE
GE
TC
GE
I
REF
I
OUT
C
OUT
t
S
V
INH
V
INL
I
INH
I
INH
I
INL
C
IN
PSS
I
CC
I
CC
I
EE
P
DISS
T
A
= +25°C
T
A
= +25°C
T
A
= +25°C
T
A
= +25°C
–2
–4
–1
–1
–4
–6
–1
–1.5
±
1.2
±
1.6
±
0.5
±
0.7
±
1.4
±
2
±
0.5
±
0.6
0.025
5
+2
+4
+1
+1.5
+4
+6
+1.5
+2
1
±
0.225
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm/°C
% FS
ppm/°C
µA
mA
pF
ns
V
V
µA
µA
µA
pF
ppm/V
mA
mA
mA
mW
Note 2
Note 2
0.003% of Full Scale
T
A
= +25°C
T
A
= +25°C
V
IN
= 5.0 V, DB0–DB10
V
IN
= 5.0 V, DB11–DB15
V
IN
= 0 V, DB0–DB15
350
2.8
10
500
2.4
625
5.0
0.8
7.5
100
1
8
V
CC
= 4.5 V to 5.5 V, V
EE
= –13 V to –17 V
All Bits HIGH
All Bits LOW
15
6
7.5
188
20
22
7.5
10
260
NOTES
1
All supplies can be varied
±
5% and operation is guaranteed. Device is tested with nominal supplies.
2
Operation is guaranteed over this reference range, but linearity is neither tested not guaranteed (see Figures 7 and 8).
Specifications subject to change without notice.
WAFER TEST LIMITS
(@ V
Parameter
CC
= +5.0 V, V
EE
= –15.0 V, I
REF
= 0.5 mA, C
COMP
= 47 F, T
A
= +25 C unless otherwise noted.)
Symbol
Conditions
DAC16G
Limit
Units
Integral Nonlinearity
Differential Nonlinearity
Zero Scale Error
Gain Error
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Positive Supply Current
Negative Supply Current
Power Dissipation
INL
DNL
ZSE
GE
V
INH
V
INL
I
IN
I
CC
I
EE
P
DISS
±
3
±
1
±
1
±
12
2.4
0.8
75
20
10
250
LSB max
LSB max
LSB max
% FS max
V min
V max
µA
max
mA max
mA max
mW max
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
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Embedded System
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